Field programmable gate array utilizing two-terminal non-volatile memory

ABSTRACT

A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

CROSS-REFERENCE

The present disclosure claims the benefit of U.S. Provisional Application No. 62/335,805, filed on May 13, 2016, entitled “FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY”, and claims priority to and is a continuation in part of U.S. patent application Ser. No. 14/335,507 filed Jul. 18, 2014, entitled “FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY”, which is a continuation-in-part of U.S. patent application Ser. No. 14/166,700 filed Jan. 28, 2014, that issued as U.S. Pat. No. 9,191,000 on Nov. 17, 2015, entitled “FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY”, which is a continuation of U.S. patent application Ser. No. 13/194,500, filed Jul. 29, 2011, that issued as U.S. Pat. No. 8,674,724 on Mar. 18, 2014, entitled “FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY”, and claims priority to and is a continuation in part of U.S. patent application Ser. No. 14/304,572 filed Jun. 13, 2014, that issued as U.S. Pat. No. 9,054,702 on Jun. 9, 2015, entitled “FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY”, which is a continuation of U.S. patent application Ser. No. 13/194,479, filed Jul. 29, 2011, that issued as U.S. Pat. No. 8,754,671 on Jun. 17, 2014, entitled “FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY”; all of the foregoing applications are hereby incorporated by reference herein in their respective entireties and for all purposes.

BACKGROUND

The present disclosure relates to devices including field programmable gate arrays. A field programmable gate array (FPGA) is an integrated circuit that can be configured after manufacturing. It is a flexible device having a great number of potential configuration modes to interact with various other hardware and software designs (e.g., on a computer motherboard). The FPGA configuration is generally specified using a hardware description language, similar to that used for an application specific integrated circuit (ASIC). Generally speaking, an FPGA can be configured to implement most or all logic functions that an ASIC could execute, yet also can be at least partially reconfigured after shipping. Coupled with relatively low design costs typically associated with ASIC design, FPGAs offer significant advantages for a wide array of electronic devices and applications.

The FPGA architecture generally comprises a set of programmable logic components, or logic blocks, and reconfigurable interconnects for selectively connecting a subset of the logic blocks with other subsets thereof. Logic blocks can be configured to execute complex algorithms, or simple logic functions like AND, NAND, NOR, etc. Most FPGAs also include memory elements that can include flip-flops, memory registers, memory arrays, or the like.

Like most integrated circuits, design goals for the FPGA include reducing minimum component size, increasing calculation speed, lowering power consumption, and others. As more applications are found for these devices, demand for improved technology comes from many sectors. Although FPGAs were largely used exclusively in telecommunications and networking in early implementations, their versatility has found these devices implemented in other industries, consumer, automotive and industrial applications.

One recent development of the general FGPA architecture was to combine embedded microprocessors with the traditional logic blocks and interconnects of the FPGA. This development has lead to what are referred to as system-on-chip or system on programmable chip devices. Many examples of system-on-chip devices have emerged, generally combining processor and analog peripheral components with the FPGA architecture. The system-on-chip has enabled the miniaturization of microprocessors to achieve a new paradigm. However, as is typical with electronics technology, new paradigms very rapidly lead to applications requiring smaller, faster or lower power devices, generating new demand for research and development.

A recent innovation for integrated circuit technology has been the concept of a resistive random access memory (RRAM). In theory, RRAM is a two-terminal, non-volatile memory technology that induces a filament (or many filaments) in a dielectric material. In a normal state, the dielectric has high resistance, and is non-conductive. However, application of a suitable voltage across the dielectric can induce a conduction path therein. Various physical mechanisms enable generation of a conduction path in a dielectric, including defects in the material (whether natural or induced via doping), metal migration, and so on. Once the filament is formed within the dielectric, it can be activated—resulting in a low resistance conduction path through the dielectric—or deactivated—rendering the dielectric a high resistance electrical insulator —through application of a suitable program or erase voltage, respectively. Thus, the conduction path can be referred to as a programmable conduction path, yielding similar electric characteristics as a conventional three-terminal transistor. In practice, however, the inventors of the present invention believe that the RRAM has not been commercially successful for reasons including incompatibility of RRAM fabrication materials with traditional CMOS processes, the incompatibility of RRAM processes as part of back end CMOS fabrication, and the like.

The inventors of the present invention believe that a basic memory cell architecture employing the RRAM technology could be a configuration of parallel bitlines intersected by perpendicular wordlines. A programmable resistance dielectric can be formed at the junction of each bitline and wordline. Such a basic memory cell would be referred to as a cross-point cell. One application of the RRAM cross-point cell, for instance, would be a block of reconfigurable interconnects within a FPGA. The RRAM cross-point cell may utilize RRAM memory cells of much smaller area than the comparable static random access memory (SRAM) counterpart. This reduction in area may lead to much greater component density. The RRAM cell also would have significantly lower power consumption, would be non-volatile memory (compared with volatile SRAM), radiation immune, would have quicker power-up, as well as other benefits. However, the inventors envision that the basic cross-point cell design may have large parasitic currents in non-activated memory cells, which may lead to slow read access. Moreover, the ratio of resistance in activated and deactivated states may not often be high enough for many sensitive applications, which might require such a ratio of 10⁶ or greater. Thus, the inventors believe that utilizing RRAM memory cells in conjunction with the FPGA technology may provide some benefits, additional improvements in particular areas will help to make the RRAM cross-point cell suitable for a wider range of applications.

SUMMARY

The following presents a simplified summary of the subject disclosure in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the disclosed subject matter. It is intended to neither identify key or critical elements of the disclosed subject matter nor delineate the scope of the subject innovation. Its sole purpose is to present some concepts of the disclosed subject matter in a simplified form as a prelude to the more detailed description that is presented later.

Various aspects of the subject disclosure provide a field programmable gate array (FPGA) utilizing two-terminal, non-volatile resistive switching memory technology. One example of such a memory is a resistive random access memory (RRAM). For simplicity of reference, RRAM is utilized throughout to refer to suitable two-terminal, non-volatile resistive switching memory cell devices operable by controlled formation and deformation of a conductive filament(s), but should not be limited to a single such device known in the art. The FPGA can comprise a switching block interconnect having signal input lines crossed by signal output lines. Disclosed configuration bits can be formed at respective intersections of the signal input lines and signal output lines.

According to particular aspects, a voltage divider for an RRAM memory cell can comprise a pull up resistor and a pull down resistor. The pull up resistor and pull down resistor comprise programmable resistance material(s), which can be programmed to a high resistance state (non-conductive) or a low resistance state (conductive). When the pull up resistor is programmed to the low resistance state, a pass gate transistor associated with the voltage divider is activated. When the pull down resistor is programmed to the low resistance state, the pass gate transistor is deactivated. Also, the voltage divider arrangement yields fast program and erase times for switching block intersections compared to conventional approaches, such as embedded Flash memories. Moreover, the RRAM memory cell of the subject disclosure yields low power consumption, significant die-size reduction and resistance or immunity to soft errors and electromagnetic radiation errors. Accordingly, various disclosed aspects provide significant improvements in FPGA technology.

According to one aspect of the invention, a field programmable gate array (FPGA) is disclosed. One apparatus includes a switching block routing array comprising a plurality of first signals and a plurality of second signals, and a transistor element coupled to the switching block routing array, wherein the transistor element comprises a gate, a first terminal and a second terminal, wherein the first terminal is coupled to a signal from the plurality of first signals, and wherein the second terminal is coupled to a signal from the plurality of second signals, and wherein the gate is configured to electrically couple the first signal to the second signal in response to a gate control signal. A device may include a plurality of resistive elements coupled to the transistor element, wherein each resistive element from the plurality of resistive elements each comprise a first electrode and a second electrode, wherein each resistive element is characterized by a plurality of resistive states including a low resistive state and a high resistive state, wherein each resistive element is characterized a polarity, wherein the polarity for each resistive element is characterized by a high resistive state in response to a first voltage applied from the first electrode to the second electrode exceeding an erase voltage and is characterized by a low resistive state in response to a second voltage applied from the second electrode to the first electrode exceeding a programming voltage, wherein the plurality of resistive elements includes a first resistive element and a second resistive element, wherein a first electrode of the first resistive element is selectively coupled to a first plurality of voltages, wherein a second electrode of the second resistive element is selectively coupled to a second plurality of voltages, wherein the plurality of resistive elements provides the gate control signal in response to a first resistive state of the first resistive element, to a second resistive state of the second resistive element, to a first voltage from the first plurality of voltages and to a second voltage from the second plurality of voltages, and a shared node coupled to a second electrode of the first resistive element, to a first electrode of the second resistive element, and to the gate of the transistor element. A system may include a programming circuit coupled exclusively to the shared node of the first resistive element and the second resistive element via an output path, wherein the programming circuit is configured to facilitate entry to the first resistive state of the first resistive element in response to a first voltage applied to the shared node, and wherein the programming circuit is configured to facilitate entry of the second resistive state of the second resistive element in response to a second voltage applied to the shared node.

According to another aspect of the invention, a method for forming a field programmable gate array (FPGA) is disclosed. One methodology includes forming a transistor element coupled to a switching block routing array comprising a plurality of signal inputs and a plurality of signal outputs, wherein the transistor element comprises a gate, a first terminal and a second terminal, wherein the first terminal is coupled to a signal input from the plurality signal inputs, and wherein the second terminal is coupled to a signal output from the plurality of signal outputs, and wherein the gate is configured to electrically couple the signal input to the signal output in response to a gate control signal, and forming a plurality of resistive elements coupled to the transistor element, wherein each resistive element from the plurality of resistive elements each comprise a first electrode and a second electrode, wherein each resistive element is characterized by a plurality of resistive states including a low resistive state and a high resistive state, wherein each resistive element is characterized a polarity, wherein the polarity for each resistive element is characterized by a high resistive state in response to a first voltage applied from the first electrode to the second electrode exceeding an erase voltage and is characterized by a low resistive state in response to a second voltage applied from the second electrode to the first electrode exceeding a programming voltage, wherein the plurality of resistive elements includes a first resistive element and a second resistive element, wherein a first electrode of the first resistive element is selectively coupled to a first plurality of voltages, wherein a second electrode of the second resistive element is selectively coupled to a second plurality of voltages, wherein the plurality of resistive elements provides the gate control signal in response to a first resistive state of the first resistive element, to a second resistive state of the second resistive element, to a first voltage from the first plurality of voltages and to a second voltage from the second plurality of voltages, wherein a shared node is coupled to a second electrode of the first resistive element, to a first electrode of the second resistive element, and to the gate of the transistor element. A process includes forming a programming circuit coupled exclusively to the shared node of the first resistive element and the second resistive element via an output path, wherein the programming circuit is configured to facilitate entry to the first resistive state of the first resistive element in response to a first voltage applied to the shared node, and wherein the programming circuit is configured to facilitate entry of the second resistive state of the second resistive element in response to a second voltage applied to the shared node.

According to yet another aspect of the invention. a process for operating an FPGA is disclosed. One technique includes coupling a first electrode of a first resistive element to a first input voltage and coupling a second electrode of a second resistive element to a second input voltage. A process includes applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.

The following description and the annexed drawings set forth in detail certain illustrative aspects of the disclosed subject matter. These aspects are indicative, however, of but a few of the various ways in which the principles of the innovation can be employed and the disclosed subject matter is intended to include all such aspects and their equivalents. Other advantages and novel features of the disclosed subject matter will become apparent from the following detailed description of the innovation when considered in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a schematic diagram of an example resistive random access memory (RRAM) configuration cell according to one or more aspects of the subject disclosure.

FIG. 2 illustrates a sample schematic diagram of a voltage divider utilized for the RRAM cell of FIG. 1 according to some aspects.

FIGS. 3A and 3B depict a schematic diagram of an example voltage divider and transistor element of the RRAM configuration cell of FIG. 1 according to further aspects.

FIG. 4 illustrates a schematic diagram of a sample programming circuit of the RRAM configuration cell of FIG. 1 in an additional aspect.

FIG. 5 depicts a block diagram of an example switching block interconnect utilizing RRAM configuration cells according to yet other aspects.

FIG. 6 illustrates a schematic diagram of an example two-by-two interconnect utilizing RRAM configuration cells according to a particular aspect.

FIG. 7 depicts a schematic diagram of an example programming operation for the two-by-two interconnect of FIG. 6 according to further aspects.

FIG. 8 illustrates a schematic diagram of another sample programming operation for the two-by-two interconnect of FIG. 6 according to another aspect.

FIG. 9 depicts a schematic diagram of an example erase operation for the two-by-two interconnect of FIG. 6 according to a further aspect.

FIG. 10 illustrates a schematic diagram of an additional sample erase operation for the two-by-two interconnect of FIG. 6 according to yet another aspect.

FIG. 11 illustrates a schematic diagram of a sample read/active mode operation for the two-by-two interconnect of FIG. 6 according to additional aspects.

FIG. 12 depicts a schematic diagram of an example RRAM configuration cell with a cell state retention circuit according to one or more aspects of the subject disclosure.

FIG. 13 depicts a schematic diagram of an example RRAM configuration cell with a storage cell and a cell state retention circuit according to one or more aspects of the subject disclosure.

FIG. 14 depicts a schematic diagram of an example RRAM configuration cell with multiple voltage divider storage cells and a cell state retention circuit according to additional embodiments of the subject disclosure.

FIG. 15 depicts a schematic diagram of an example RRAM configuration cell with multiple storage cells and a cell state retention circuit according to still other embodiments of the subject disclosure.

FIG. 16 depicts a flowchart of an example method for fabricating a field programmable gate array (FPGA) utilizing RRAM technology according to some aspects.

FIG. 17 illustrates a flowchart of a sample method for fabricating a switching block interconnect utilizing RRAM memory in other aspects.

FIG. 18 depicts a flowchart of an example method for fabricating a field programmable gate array (FPGA) utilizing RRAM technology according to some aspects.

FIG. 19 depicts a flowchart of an example method for fabricating a field programmable gate array (FPGA) utilizing RRAM technology according to some aspects.

FIG. 20 depicts a flowchart of an example method for fabricating a field programmable gate array (FPGA) utilizing RRAM technology according to some aspects.

FIG. 21 depicts a flowchart of an example method for fabricating a field programmable gate array (FPGA) utilizing RRAM technology according to some aspects.

FIG. 22 illustrates a flowchart of a sample method for fabricating a switching block interconnect utilizing RRAM memory in other aspects.

FIG. 23 depicts a block diagram of an example electronic operating environment according to one or more aspects of the subject disclosure.

DETAILED DESCRIPTION

The disclosed subject matter is described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout the description. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the subject innovation. It may be evident, however, that the disclosed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram or schematic form in order to facilitate describing the subject innovation.

As utilized herein, terms “component,” “system,” “architecture” and the like are intended to refer to a computer or electronic-related entity, either hardware, a combination of hardware and software, software (e.g., in execution), or firmware. For example, a component can be one or more transistors, a memory cell, an arrangement of transistors or memory cells, a gate array, a programmable gate array, an application specific integrated circuit, a controller, a processor, a process running on the processor, an object, executable, program or application accessing or interfacing with semiconductor memory, a computer, or the like, or a suitable combination thereof. The component can include erasable programming (e.g., process instructions at least in part stored in erasable memory) or hard programming (e.g., process instructions burned into non-erasable memory at manufacture).

By way of illustration, both a process executed from memory and the processor can be a component. As another example, an architecture can include an arrangement of electronic hardware (e.g., parallel or serial transistors), processing instructions and a processor, which implement the processing instructions in a manner suitable to the arrangement of electronic hardware. In addition, an architecture can include a single component (e.g., a transistor, a gate array, . . . ) or an arrangement of components (e.g., a series or parallel arrangement of transistors, a gate array connected with program circuitry, power leads, electrical ground, input signal lines and output signal lines, and so on). A system can include one or more components as well as one or more architectures. One example system can include a switching block architecture comprising crossed input/output lines and pass gate transistors, as well as power source(s), signal generator(s), communication bus(ses), controllers, I/O interface, address registers, and so on. It is to be appreciated that some overlap in definitions is anticipated, and an architecture or a system can be a stand-alone component, or a component of another architecture, system, etc.

In addition to the foregoing, the claimed subject matter can be implemented as a method, apparatus, or article of manufacture using typical manufacturing, programming or engineering techniques to produce hardware, firmware, software, or any suitable combination thereof to control an electronic device to implement the disclosed subject matter. The terms “apparatus” and “article of manufacture” where used herein are intended to encompass an electronic device, a semiconductor device, a computer, or a computer program accessible from any computer-readable device, carrier, or media. Computer-readable media can include hardware media, or software media. In addition, the media can include non-transitory media, or transport media. In one example, non-transitory media can include computer readable hardware media. Specific examples of computer readable hardware media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips . . . ), optical disks (e.g., compact disk (CD), digital versatile disk (DVD) . . . ), smart cards, and flash memory devices (e.g., card, stick, key drive . . . ). Computer-readable transport media can include carrier waves, or the like. Of course, those skilled in the art will recognize many modifications can be made to this configuration without departing from the scope or spirit of the claimed subject matter.

Field programmable gate arrays (FPGAs) are employed in a wide range of electronic technology, serving as reconfigurable systems. In some applications, FPGAs can be integrated with microprocessors to serve as system-on-chip devices, which can be employed as a primary controller for various computer components, such as set top boxes and others. A wide range of uses for these devices exist, including telecommunications and networking, robotics, micro-electronics, small-scale industrial manufacturing, consumer electronics including handset computers, smart-phones and personal digital assistants, and the like, as well as other applications and technologies. Additionally, new applications are invented routinely as capabilities of FPGA and FPGA-based devices improve.

One basic FPGA architecture is the programmable switching block, which acts as a programmable signal routing matrix. A switching block comprises a set of parallel signal input lines intersected by a set of perpendicular signal output lines. At a junction of respective signal input lines and signal output lines is a configuration cell (also referred to herein as a configuration bit). Activation and deactivation of subsets of configuration cells at respective signal input/signal output junctions facilitate configuration of a programmable switching block. Particularly, a configuration cell at a given junction can be activated to electrically connect or route a signal input line to a signal output line at that junction, or can be deactivated to electrically isolate the signal input line and signal output line at that junction. The ability to activate or deactivate respective junctions is the basis for configurability of the programmable switching block. Thus, for instance, a set of electrical components connected to the signal inputs and signal outputs can be selectively inter-connected by activating particular junctions and deactivating other junctions. This selective inter-connection can enable some functionality, while disabling other functionality, in effect configuring the programmable switching block for the enabled functionality (which is a subset of all possible functionality thereof).

One of the more common FPGA configuration cells is the SRAM configuration cell. Probably the most typical SRAM configuration cell comprises six or more transistors, referred to as a 6T SRAM cell. Four of the SRAM transistors form a pair of cross-coupled inverters, or latches. The SRAM cell has two stable states that denote respective states of a binary bit, 0 and 1. The remaining two transistors of the 6T SRAM cell control access to a storage cell during read and write operations, and are referred to as access transistors.

In addition to the basic 6T SRAM, other SRAM chips use eight transistors, ten transistors or more to store a single bit. Generally, the fewer transistors needed per cell the smaller the cell and the lower the cost of manufacture. The relatively large area of the 6T SRAM cell (often greater than 125 F²—where F denotes the minimum feature size, such as 65 nanometer, etc.) increases cost of manufacture while reducing transistor density, as compared with technologies having smaller component size. In addition, SRAM is volatile memory, requiring continuous power to maintain stored information, and is susceptible to memory loss from high frequency electromagnetic radiation (e.g., cosmic rays, high frequency ultraviolet, X-Ray, etc.). Moreover, a system designed with SRAM based FPGA typically requires external Flash memory to configure the SRAM bits during powerup sequence, slowing down the powerup sequence, and further adding to manufacture costs and increasing chip size.

Aspects of the subject disclosure provide alternatives to SRAM memory for FPGA configuration cells, or alternatives to configuration cells comprised exclusively of SRAM memory or other volatile switches, in various embodiments. In one aspect, a programmable switching block is formed from resistive random access memory (RRAM), rather than SRAM memory. RRAM technology is based on dielectric material having programmable resistance (e.g., a resistance that can be altered between two or more states by application of an external force, such as a voltage). A simple RRAM memory cell can include a programmable resistance dielectric—having programmable high resistance and low resistance states—positioned between two otherwise isolated conductors. Thus, this simple RRAM memory cell can be conducting or non-conducting in response to a program voltage, mimicking the basic property of a pass gate transistor.

RRAM memory cells have several advantages over SRAM memory cells. First, RRAM technology is generally much smaller than SRAM, consuming silicon area on the order of 4 F² per adjacent RRAM device (e.g., a memory cell comprising two RRAM devices would therefore be approximately 8 F² if constructed in adjacent silicon space). Non-adjacent RRAM devices, e.g., stacked above or below each other, can consume as little as 4 F² for a set of multiple non-adjacent devices. This leads to much greater semiconductor component density, and lower manufacturing costs for a given number of transistors. Like SRAM, RRAM also has fast programming speed and low programming current, but unlike SRAM has high logic utilization. Further, RRAM is non-volatile memory; RRAM has the capacity to store data without continuous application of power. Therefore, RRAM based FPGAs utilizing non-volatile embedded RRAM as configuration bits can have a much faster power up cycle than the SRAM FPGAs, since external non-volatile memory is generally not required. In addition to the foregoing, RRAM cells can generally be built between metal interconnect layers, enabling RRAM FPGAs to be usable for two-dimension as well as three-dimension FPGA architectures.

One simple RRAM programmable switching block arrangement is called a RRAM cross-point cell. The RRAM cross-point cell comprises a dielectric material having discrete programmable resistances positioned at a signal junction of a programmable switching block (e.g., between a signal input line and a signal output line). The RRAM cross-point cell can operate as a configuration cell or configuration bit for the signal junction, as described herein. For instance, when activated the RRAM cross-point cell can configure the signal junction to pass a signal (e.g., when a programmable resistance of the RRAM cross-point cell is programmed to a low resistance state), and when deactivated the RRAM cross-point cell can configure the signal junction to block the signal (e.g., when the programmable resistance is erased, and in a high resistance state). Thus, the cross-point cell comprises a simple RRAM dielectric that acts as a switching device between the signal input and signal output. Generally, the cross-point cell is programmed or erased by application of a suitable program or erase voltage to the signal lines.

Although the RRAM cross-point cell is a simple device, it has some drawbacks relative to metal oxide semiconductor (MOS) or complementary metal oxide semiconductor (CMOS) configuration cells. First, a resistance value of a typical RRAM when on or programmed (also referred to as the on resistance, or R_(on)) is usually higher than a MOS transistor's resistance, in a similar programmed state. This means that a signal will propagate more slowly through a signal intersection activated with an RRAM configuration cell based on the simple cross-point cell, as compared to a MOS or CMOS-based configuration cell. In addition, typical RRAM cross-point cells often have lower erase resistance (also referred to as off resistance, or R_(off)) than typical MOS or CMOS transistors. This lower R_(off), can result in a sizable parasitic signal through the signal intersection when the RRAM cross-point cell is erased. A MOS Roff/Ron ratio (also referred to herein as a cutoff ratio) is usually more than 10⁶, while some RRAM can reliably deliver cutoff ratios of up to 10³, but are less reliable above that quantity (though two-terminal resistive switching memory devices like RRAM currently in development by the assignee of the present disclosure have demonstrated higher and reliable cutoff ratios). Thus, FPGA configuration cells implemented exclusively with the RRAM cross-point cell as a switching device may be unsuitable for applications requiring higher cutoff ratios, unless the cutoff ratio is improved to reasonably match typical cutoff ratios of MOS or CMOS transistors. Therefore, FPGA manufacturers are limited for many applications to a MOS or CMOS based switching transistor (pass gate transistor), connected to an SRAM cell to activate and deactivate the switching transistor.

Additional aspects of the subject disclosure provide an RRAM-based configuration cell having a significantly higher activation/deactivation resistance ratio (cutoff ratio), in conjunction with a die size much smaller than SRAM configuration cells. In some aspects, an RRAM configuration cell is provided having a plurality of resistive elements and one or more transistor elements. In one such aspect, the resistive elements can form a voltage divider having a common node that drives a gate of a pass gate transistor. Moreover, the pass gate transistor can include a transistor having a cutoff ratio on the order of 10⁶ or greater. In at least one aspect, the pass gate transistor can comprise a CMOS transistor.

Other embodiments of the present disclosure incorporate smaller improvements to die size as compared with the foregoing embodiments, yet also deliver significantly reduced power consumption. These embodiments can be preferable, for instance, where very low power consumption is desirable for an FPGA device, separate from or in addition to reduced die size relative to large SRAM configurations (e.g., 6T or 8T SRAM configurations). As is described in more detail herein, some such embodiments integrate non-volatile memory devices into latch programming circuitry. Further, these non-volatile memory devices can be isolated from power except in conjunction with a memory operation (e.g., to program, read or erase the non-volatile memory device), or to program an associated latch of an FGPA configuration cell.

According to further aspects, the RRAM-based configuration cell comprises programming circuitry that is independent of signal input and signal output lines of an associated FPGA programmable switching block. The independent programming circuitry can improve input signal to output signal propagation performance since the programming circuits are not generating additional load capacitance and leakage on the input signal and output signal lines. In a particular aspect, the programming circuitry can include a transistor element that facilitates complementary programming of resistive elements of a voltage divider. The complementary programming can in turn drive alternate states of a pass gate transistor, activating or deactivating the pass gate transistor.

The RRAM-based configuration cell can yield significant advantages over other programmable switching blocks implemented with simple RRAM cross-point cells. For instance, because input signal lines and output signal lines of an FPGA are connected or isolated by a pass gate transistor having a high cutoff ratio, rather than an RRAM dielectric with 10³ cutoff ratio, high speed applications can be served with good noise immunity. Moreover, better signal integrity and disturb immunity can be achieved because the signal path is not routed through the RRAM cell. Because programming circuitry is independent of the signal lines, related signal degradation can be mitigated or avoided.

Referring now to the drawings, FIG. 1 illustrates a schematic diagram of an example RRAM configuration cell 100 according to various aspects of the subject disclosure. RRAM configuration cell 100 can be employed as a component of various electronic systems and architectures, including a FPGA device. In at least one aspect of the subject disclosure, RRAM configuration cell 100 can be employed for a programmable switching block, for instance, involved with activating or deactivating signal input and output junctions thereof. Further, RRAM configuration cell 100 can be relatively small. For instance, transistor element 102 can be about 10-12 F² (e.g., 11 F²) and programming circuit 106 can be about an additional 12 F² in size. While voltage divider 104 can be approximately 8 F² in size in some disclosed aspects, in at least one aspect of the subject disclosure voltage divider 104 can be constructed over (or under) programming circuit 106 or over (or under) transistor element 102, so as to not add additional area to programming circuit 106. Thus, RRAM configuration cell 100 including programming circuit 106, voltage divider 104 and transistor element 102 can be about 24 F² in size. In a particular aspect, transistor element 102 and voltage divider 104 can consume about 11 F² of silicon space (e.g., where voltage divider 104 is fabricated above or below transistor element 102 in the silicon space), and in an alternative aspect programming circuit 106 and voltage divider 104 can consume about 12 F² of silicon space in a similar manner. When compared to a similar SRAM memory cell having 6 transistors to control the gate of transistor element 102, in addition to a programming transistor(s), with size of 120 F² or more, RRAM configuration cell 100 is relatively small. (Note that F is defined as a minimum feature size, e.g., 130 nanometer, 90 nanometer, 65 nanometer, 45 nanometer, 32 nanometer, and so on, of the fabrication technology employed to generate the cell).

RRAM configuration cell 100 can comprise a transistor element 102. Transistor element 102 can comprise a gate-driven transistor having relatively high cutoff ratio. Examples of transistor element 102 can include an NMOS transistor, a PMOS transistor, or a CMOS transistor (e.g., an NMOS+PMOS transistor), or other suitable three-terminal transistor. In at least one aspect of the subject disclosure, transistor element 102 can be selected for suitable electrical characteristics, including switching speed, power consumption, cutoff ratio (e.g., about 10⁶, about 10⁷, or greater), or the like, or a suitable combination thereof. The electrical characteristics can be matched to an anticipated application or group of applications in which RRAM configuration cell 100 is intended for use.

Further, transistor element 102 has at least a gate and a channel region. The gate of transistor element 102 can be driven by a common node of a voltage divider 104. Voltage divider 104 therefore controls activation/deactivation states of transistor element 102. In at least one aspect of the subject disclosure, voltage divider 104 can be a programmable voltage divider. Particularly, voltage divider 104 can comprise two programmable resistive elements (e.g., first programmable resistive element 104A, second programmable resistive element 104B) having respective programmable resistances. For instance, the resistive elements 104A, 104B can have at least a first programmable resistance and a second programmable resistance, where the second programmable resistance is a different resistance value from the first programmable resistance. In a first aspect of the subject disclosure, the first and second programmable resistive elements 104A, 104B can be programmed or erased to have the first and second programmable resistances, respectively (e.g., low resistance and high resistance). In a second aspect, the first and second programmable resistive elements 104A, 104B can be erased or programmed to have the second and first programmable resistances, respectively (e.g., high resistance and low resistance). In a third aspect, the first and second programmable resistive elements 104A, 104B can be erased to the second programmable resistance (e.g., both high resistance). In a fourth aspect, the first and second programmable resistive elements 104A, 104B can be programmed to have the first programmed resistance (e.g., both low resistance).

One operational example for voltage divider 104 is as follows. The first programmable resistive element 104A can be programmed to a low resistance and the second programmable resistive element 104B can be erased to a high resistance. This state can be utilized, for instance, to activate or to turn on transistor element 102. In another state, the first programmable resistive element 104A can be erased to a high resistance and the second programmable resistive element 104B can be programmed to a low resistance. This state can be utilized, for instance, to turn off transistor element 102. In yet another state, both the first programmable resistive element 104A and the second programmable resistive element 104B can be erased to the high resistance state. This third state can be utilized, for instance, as an intermediate state while changing resistance states (e.g. from high to low or low to high). In at least one aspect, the third state can also serve as a suitable initial factory setting.

The programmable resistance of voltage divider 104 determines whether a positive source voltage (not depicted) is applied to the gate of transistor element 102 (activating transistor element 102), or whether ground or its equivalent is applied to the gate of transistor element 102 (deactivating transistor element 102). Accordingly, the program state of voltage divider 104 determines activation/deactivation state of transistor element 102.

A programming circuit 106 is depicted for RRAM configuration cell 100. As depicted, programming circuit 106 can be independent of signal lines of associated communication circuitry (e.g., signal input and signal output lines of a programmable switching block). Programming circuit 106 can include at least one program transistor that, in conjunction with pull up and pull down voltage sources (not depicted), can program the resistive elements of voltage divider 104. In at least one aspect, programming circuit 106 can be operated to program the resistive elements in a complementary fashion, as is described in more detail herein (e.g., see FIGS. 2, 3A, 3B and 6, infra).

As depicted, in FIG. 1, transistor element 102 can be electrically connected to a signal output line 108 and a signal input line 110. Thus, activating transistor element 102 can enable conductivity between signal output 108 and signal input 110. Likewise, deactivating transistor element 102 can electrically isolate signal output 108 from signal input 110. In this manner, transistor element 102 acts as a pass gate transistor with respect to the electrical junction of signal input 110 and signal output 108. In similar arrangements, RRAM configuration cell 100 can be utilized for configuring or re-configuring a programmable switching block. Particularly, by forming respective RRAM configuration cells 100 at respective input/output junctions of the switching block, and controlling the activation/deactivation of these RRAM configuration cells 100, configuration of the respective input/output junctions can be accomplished, as is described in more detail herein (e.g., see FIG. 5, infra).

FIG. 2 depicts a schematic diagram of an example voltage divider circuit 200 according to further aspects of the subject disclosure. In at least one aspect, voltage divider circuit 200 can be substantially similar to voltage divider 104 of FIG. 1, supra. Particularly, voltage divider circuit 200 can be configured to drive a transistor element of an RRAM configuration cell, as described herein.

Voltage divider circuit 200 can comprise a first resistive element, resistive element₁ 202 and a second resistive element, resistive element₂ 204. As depicted, resistive element₁ 202 and resistive element₂ 204 are arranged electrically in series. Additionally, resistive elements 202 and 204 can have programmable resistance values.

In some aspects of the subject disclosure, resistive elements 202 and 204 can be formed of a suitable dielectric material that can be programmed to have two or more discrete resistance values. In one particular aspect, resistive element₁ 202 and resistive element₂ 204 are comprised of the same dielectric material and have substantially the same two or more discrete resistance values. In another aspect, resistive element₁ 202 and resistive element₂ 204 can be comprised of different dielectric materials, or can have different discrete resistance values, or a combination thereof.

According to at least one aspect of the subject disclosure, resistive element₁ 202 can serve as a pull up resistor for a RRAM configuration cell, whereas resistive element₂ 204 can serve as a pull down resistor for the RRAM configuration cell. Further, the pull up resistor has a first programmable resistance that can be programmed at least to a first resistance value or a second resistance value, where the first resistance value is smaller than the second resistance value. Moreover, the pull down resistor has a second programmable resistance. In at least one aspect of the subject disclosure, the second programmable resistance can be set at least to a third resistance value or a fourth resistance value. In a particular aspect, the third resistance value of the pull down resistor can be substantially equal to the first or second resistance value (of the pull up resistor), or the fourth resistance value of the pull down resistor can be substantially equal to the first or second resistance values, or a suitable combination thereof.

In other aspects, a ratio of respective resistance values of the pull up resistor and pull down resistor can determine a cutoff ratio of the respective resistors. A general convention for the cutoff ratio is to divide a higher of the programmable resistances by a lower of the programmable resistances (e.g., 1 giga-ohms/100 kilo-ohms). For instance, a cutoff ratio of the pull up resistor can be equal to the first resistance value divided by the second resistance value, whereas a cutoff ratio of the pull down resistor can be equal to the third resistance value divided by the fourth resistance value. In a particular aspect, resistive element₁ 202 or resistive element₂ 204 can have a cutoff ratio at least of 10³. In one aspect, one or more of the cutoff ratios can be 10⁴ or more, and in yet another aspect, one or more of the cutoff ratios can be 10⁵ or more.

In various embodiments, resistive elements such as resistive elements 202 and 204 are bipolar switching devices associated with a low resistance state in response to a signal of a first polarity (e.g., a transition to the low resistance state when initially in a high resistance state), and associated with the high resistance state in response to a signal of a second polarity (e.g., a transition to the high resistance state when initially in the low resistance state). (In various embodiments, conduction of current and the low resistance state may be caused by formation of a conductive filament within the resistive element, or the like, whereas resistance to current and the high resistance state may be caused by deformation or a break in continuity of the conductive filament;) Within voltage divider circuit 200, an orientation of resistive elements 202 and 204 with respect to pull up contact 208, program contact 206 and pull down contact 210 can affect how resistive elements 202 and 204 change state in response to signals applied at pull up contact 208, program contact 206 and pull down contact 210. This orientation is referred to herein as a polarity configuration, and is based upon the structure of the resistive element.

As an illustrative example of forward and reverse polarity configurations, under a first polarity configuration (e.g. a forward polarity configuration in which pull up contact 208 is a first terminal for resistive element 202 and program contact 206 is a second terminal for resistive element 202), a positive voltage applied at the first terminal (pull up contact 208) relative the second terminal (program contact 206) of resistive element 202 may cause the resistive element to enter the low resistance state, and a positive voltage (e.g., an erase voltage) applied at the second terminal of resistive element 202 relative to the first terminal may cause the resistive element to enter the high resistance state. Under a second polarity configuration (e.g. a reverse polarity configuration, where the structure of the resistive element is oriented differently vis-à-vis program contact 206 and pull up contact 208, compared with the forward polarity configuration), a positive voltage applied at the second terminal relative the first terminal of the resistive element 202 may cause the resistive element 202 to enter the low resistance state, whereas the positive voltage applied at the first terminal relative the second terminal may cause the resistive element 202 to enter the high resistance state. Likewise, resistive element 204 can have the forward polarity configuration (e.g., programmed to low resistance in response to positive voltage applied at program contact 206; erased to high resistance in response to positive voltage applied to pull down contact 210) or the reverse polarity configuration (e.g., erased in response to positive voltage applied to program contact 206, and programmed in response to positive voltage applied to pull down contact 210).

In various embodiments resistive elements 202 and 204 will be oriented with the same polarity configuration (e.g. both forward polarity configuration—programmed in response to positive voltage applied at pull up contact 208 and program contact 206, respectively—or both reverse polarity configuration—programmed in response to positive voltage applied at program contact 206 and pull down contact 210, respectively). In other embodiments, the polarities may be different for resistive elements 202 and 204. Thus, resistive element 202 can have the forward polarity configuration and resistive element 204 can have the reverse polarity configuration, or vice versa, according to various embodiments. Accordingly, various embodiments of the present invention disclosed herein will have different behavior depending upon structure or polarity configurations of the resistive elements. For instance, while the operations of FIGS. 7-10, infra, illustrate embodiments wherein the resistive elements of the depicted voltage dividers are both in the reverse polarity configuration (as described above), other embodiments in which one or both of the resistive elements have the forward polarity configuration, and the associated variations to their respective program and erase operations that would be known to one of ordinary skill in the art or made known by way of the context provided herein, are considered within the scope of the subject disclosure.

In some embodiments, the pull up resistor and pull down resistor can be programmed in a complementary fashion, such that when the pull up resistor is programmed to the first resistance value (R_(PU) ON—conducting state for R_(PU)), the pull down resistor is erased to the second resistance value (R_(PD) off—non-conducting state for R_(PD)), and vice versa. Complementary programming can be implemented, for instance, where the pull up resistor and the pull down resistor have the same polarity configuration (whereas separate or sequential programming—programming only one resistor, or first programming one and then erasing the second resistor—may be utilized where the pull up resistor and pull down resistor have different polarity configurations, as suitable). Resistive elements 202 and 204 can be set to a particular resistance value by application of a suitable voltage across the respective resistance elements 202 and 204. For instance, resistive elements 202 and 204 can be set to R_(PU) ON (low resistance, conducting state) or R_(PD) ON, respectively, upon application of the voltage to the pull up resistor or the pull down resistor, respectively. If an erase voltage is applied to the pull up resistor or pull down resistor, these resistors will have the R_(PU) OFF (e.g., the second resistance value) or R_(PD) OFF (e.g., the fourth resistance value), respectively. Said differently, programming either resistor to the low resistance, conducting state can be accomplished by applying a program voltage to the resistor, whereas the respective resistors are in a high resistance, non-conductive state when an erase voltage is applied thereto (whether for unipolar or bipolar RRAM).

Voltage can be applied to the pull up resistor and pull down resistor via three voltage contacts, a program contact 206, pull up contact 208 and pull down contact 210. Moreover, the three voltage contacts can be operated to program the resistive elements 202 and 204 in a complementary fashion. Particularly, by applying substantially the same voltage at the program contact 206 and one other of the two contacts (208, 210), a substantially zero voltage drop can be applied across one of the resistive elements. Further, by applying a second voltage having a difference in magnitude of at least the program voltage, the remaining of the two resistive elements observes the program voltage (in a forward polarity configuration) or the erase voltage (reverse polarity configuration). As a more specific example, applying the program voltage to both program contact 206 and pull up contact 208 results in substantially no voltage drop across resistive element₁ 202, rending the pull up resistor un-programmed. Applying zero volts (or ground) at the pull down contact 210 then causes a voltage drop substantially equivalent to the program voltage across resistive element₂ 204, thus programming the pull down resistor (in a forward polarity configuration) to be in a low resistance state. When the resistive element 204 is in reverse polarity configuration, the voltage drop is substantially equivalent to an erase voltage, thus the pull down resistor is erased and in a high resistance state.

In contrast, application of high voltage at pull up contact 208, zero voltage at pull down resistor 210 and zero voltage at program contact 206 results in programming of the pull up resistor 202 (in a forward polarity configuration) (which observes program voltage at pull up contact 208 and zero volts at program contact 206) to be in a low resistance state and non-programming of the pull down resistor (which observes zero volts at both pull down contact 210 and program contact 206). When the resistive element 202 in in reverse polarity configuration, the voltage drop may be substantially equivalent to an erase voltage, thus even if the pull up resistor 202 is erased and in a high resistance state.

In the foregoing example, it can be understood that complementary programming of an initially erased pull up resistor and initially erased pull down resistor can be accomplished by tying pull up contact 208 to the program voltage (e.g., three volts), and tying pull down contact 210 to zero volts, and simply applying program contact 206 to zero volts or to the program voltage. Under a forward polarity configuration, zero volts on contact 206 will program the pull up resistor (resistive element₁ 202), and program voltage on contact 206 will program the pull down resistor (resistive element₂ 204) in this configuration. This is only one example implementation, however, and is not intended to limit the scope of the subject disclosure. Under a reverse polarity configuration, zero volts on contact 206 will erase the pull up resistor (resistive element₁ 202), and program voltage on contact 206 will erase the pull down resistor (resistive element₂ 204). Regardless of how complementary programming is implemented, voltage divider 200 results in distinct voltages at cell gate contact 212, depending on respective states of the pull up resistor and pull down resistor. These distinct voltages can configure a pass gate transistor to be active or inactive. For instance, where pull up contact 208 is set to the program voltage and pull down contact 210 is set to zero volts, activating the pull up resistor (to be in a low resistance state) and deactivating the pull down resistor (to be in a high resistance state) results in charging up cell gate contact 212; in effect passing the positive voltage source applied at node 208 to cell gate contact 212. In RRAM configuration cell 100 of FIG. 1, for instance, this could activate transistor element 102 having a gate electrically connected to cell gate contact 212. In contrast, erasing the pull up resistor (to be in a high resistance state) and programming the pull down resistor (to be in a low resistance state) causes charging down of cell gate contact 212 and thereby deactivating any transistor gate connected to cell gate contact 212.

FIGS. 3A and 3B illustrate alternate program states of a two-resistor, single transistor memory cell according to further aspects of the subject disclosure. Particularly, FIG. 3A illustrates a closed transistor, or conducting state of the memory cell. In contrast, FIG. 3B depicts an open transistor, or non-conducting state of the memory cell. Referring first to FIG. 3A, circuit 300A comprises a first resistive element 302A and a second resistive element 304A arranged electrically in serial. Resistive elements 302A and 304A have multiple discrete programmable resistances. For instance, resistive elements 302A and 304A can be formed of one or more RRAM dielectrics that can be programmed to a first discrete programmable resistance (e.g., a program resistance) upon application of a suitable voltage thereto (e.g., a program voltage), and to a second discrete programmable resistance (e.g., an erase resistance) upon application of another suitable voltage (e.g., an erase voltage). It should be appreciated that different RRAM technologies exist, having different discrete programmable resistances, and different associated program/erase voltage. For instance, a unipolar RRAM, once initially programmed, can be later programmed in response to a first positive voltage (e.g., three volts) and erased in response to a second positive voltage (e.g., between four and five volts). Bipolar RRAM, on the other hand, becomes programmed in response to a positive voltage and erased in response to a negative voltage. Where no specific RRAM technology or program/erase voltage is specified for the various aspects and embodiments herein, it is intended that such aspects and embodiments incorporate any suitable RRAM technology and be operated by program/erase voltages appropriate to that RRAM technology, as would be known by one of ordinary skill in the art or made known by way of the context provided herein.

In addition to the foregoing, circuit 300A has a transistor 306A comprising a gate 308B and a channel region. Transistor 306A can be a suitable three-terminal transistor device (e.g., an NMOS, a PMOS or a CMOS transistor). As depicted, gate 308A can be driven by a common node 310A of resistive elements 302A and 304A. Additionally, first resistive element 302A is connected to voltage contact 312A, having a voltage value suitable for programming resistive element 302A to a low resistance state, also referred to as activating resistive element 302A. Resistive element 304A, on the other hand, is connected to a voltage contact 314A having low voltage (e.g., ground, a negative voltage, or other suitable voltage lower than the voltage applied at voltage contact 312A), as indicated.

As depicted, resistive element 302A is programmed, having low resistance. Being complementary, resistive element 304A is erased, having high resistance. Accordingly, a program voltage generated at voltage contact 312A can drive common node 310A, thereby activating transistor 306A. Thus, transistor 306A is in the conducting state. In various embodiments, when resistive element 302A and 304A are in a forward polarity configuration, the voltage across resistive element 302A is small, whereas the voltage across resistive element 304A may be closer to a programming voltage. The inventors recognize that in some rare conditions, the voltage across resistive element 304A may be high enough to be a programming voltage and to change the high resistance state of resistive element 304A to a low resistance state. Accordingly, in various embodiments, when resistive element 302A and 304A are in a reverse polarity configuration, the voltage across resistive element 302A is small, whereas the voltage across resistive element 304A may be closer to an erase voltage. The inventors recognize that if the voltage across resistive element 304A is high enough to be an erase voltage the high resistance state of resistive element 304A will more readily remains in a high resistance state.

FIG. 3B illustrates a circuit 300B in an inactive state (where transistor 306B is turned off). Circuit 300B has the same general architecture as circuit 300A, including a first resistive element 302B and a second resistive element 304B arranged electrically in serial. A transistor 306B has a gate 308B connected to a common node 310B of first resistive element 302B and second resistive element 304B. Furthermore, first resistive element 302B is connected to voltage contact 312B having a program voltage applied thereto (e.g., a high positive voltage), and second resistive element 304B is connected to a voltage contact 314B having low voltage (e.g., ground).

Different from circuit 300A, first resistive element 302B has high resistance (e.g., erased) whereas second resistive element 304B has low resistance (e.g., programmed). This can be accomplished, for instance, by applying high voltage 312B at common node 310B. Thus, first resistive element 302B experiences substantially no voltage drop, whereas second resistive element 304B experiences a voltage drop substantially equal to the voltage applied at voltage contact 312B (e.g., the program voltage). Accordingly, current can flow to voltage contact 314B, thus programming the pull down resistor to a low resistance state. During read operation, V_(CC) is applied to voltage contact 312B, and ground is applied to voltage contact 314B, draining charge from gate 308B. This in turn deactivates transistor 306B, rendering transistor 306B in the non-conducting state. As described, circuit 300A and circuit 300B can depict alternate states of RRAM configuration cell 100, in at least one aspect of the subject disclosure.

In various embodiments, when resistive element 302B and 304B are in a forward polarity configuration, the voltage across resistive element 304B is small, whereas the voltage across resistive element 302B may be closer to a programming voltage. The inventors recognize that in some rare conditions, the voltage across resistive element 302B may be high enough to be a programming voltage and to change the high resistance state of resistive element 302B to a low resistance state. Accordingly, in various embodiments, when resistive element 302B and 304B are in a reverse polarity configuration, the voltage across resistive element 304B is small, whereas the voltage across resistive element 302B may be closer to an erase voltage. The inventors recognize that if the voltage across resistive element 302B is high enough to be an erase voltage the high resistance state of resistive element 302B will more readily remains in a high resistance state.

FIG. 4 illustrates a schematic diagram of a sample programming circuit 400 according to still other aspects of the subject disclosure. Programming circuit 400 can be utilized during programming and erasing of an RRAM configuration cell, but is generally not active during standby or read operations. In at least one aspect, programming circuit 400 can be substantially similar to programming circuit 106 of FIG. 1, supra. However, neither programming circuit 106 nor programming circuit 400 is limited to this aspect.

As depicted, programming circuit 400 can comprise a program transistor 402. Program transistor 402 can be any suitable switching transistor or pass gate transistor device. In one aspect of the subject disclosure, program transistor 402 can comprise a three-terminal transistor device. Additionally, programming circuit 400 can comprise a row programming contact 404 connected to a gate of program transistor 402. By applying a suitable positive voltage to row programming contact 404, program transistor 402 is activated. By applying a lesser voltage, or ground, to row programming contact 404, program transistor 402 is deactivated.

Further to the above, programming circuit 400 can comprise a column programming contact 406. Column programming contact 406 is connected to a channel region of program transistor 402. This arrangement causes a voltage applied at column programming contact 406 to be propagated to program contact 408 when program transistor 402 is activated, as described above, and causes column programming contact 406 to be isolated from program contact 408 when program transistor 402 is deactivated (e.g., during a read or standby operation). Where program contact 408 is connected to one or more programmable resistances, programming circuit 400 can facilitate programming (or erasing) the programmable resistance(s). This can be accomplished in part by first activating program transistor 402 and then applying a suitable program voltage at column programming contact 406. This program voltage is propagated to program contact 408 by programming circuit 400, applying at least one voltage to one or more of the programmable resistances.

According to a particular aspect of the subject disclosure, program contact 408 can be substantially equivalent to program contact 206 of FIG. 2, or substantially equivalent to common node 310A or 310B of FIG. 3A or 3B, respectively. In this case, one example implementation of programming circuit 400 can be to program or erase respective programmable resistor elements of a voltage divider to respective program or erase states. Thus, a voltage propagated to program contact 408 from column programming contact 406 is also observed at the common node of the voltage divider. When appropriate voltages are also applied to respective dedicated nodes associated with the voltage divider, the voltage divider can be programmed to different states by programming circuit 400, as described in FIGS. 3A and 3B, supra.

As a particular example, consider the case where programming circuit 400 is connected to common node 310A/310B of FIGS. 3A and 3B. To activate programming circuit 400, a program voltage is applied to row programming contact 404, which activates program transistor 402. The activated program transistor 402 passes a voltage applied at column programming contact 406 to program contact 408. To program the pull down resistor (depicted at FIG. 3B), a program voltage (e.g., high positive voltage) is applied at column programming contact 406, and low voltage (e.g., ground, zero volts, etc.) is applied at contact 314B. To program the pull up resistor (FIG. 3A), the low voltage is applied to column programming contact 406 and the program voltage is applied to high voltage (contact) 312A. To erase the pull up resistor once it is programmed (e.g., resistive element 302A), the program voltage is applied to column programming contact 406 while ground is applied to voltage contact 312A. Likewise, to erase the pull down resistor once it is programmed (e.g., resistive element 304B), the program voltage is applied to voltage contact 314B and ground is applied to column programming contact 406.

The programming and erasing of pull up and pull down resistors described above can in turn drive activation/deactivation of a pass transistor having its gate connected to program contact 408 (e.g., transistor 306A transistor 306B, transistor element 102, etc.). Specifically, programming circuit 400 can be utilized in part to program or erase pull up and pull down resistors, which in turn control activation/deactivation of the pass gate transistor. This controlled activation/deactivation of the pass gate transistor provides one mechanism for configuring the programmable switching block junction.

FIG. 5 illustrates a block diagram of an example programmable switching block 500 according to further aspects of the subject disclosure. According to particular aspects, programmable switching block 500 can be programmed via RRAM-based memory cells. In at least one such aspect, the RRAM-based memory cells can be described substantially according to memory cell 100. In another aspect, the RRAM-based memory cells can be described by a combination of voltage divider 200, programming circuit 400, and pass gate transistor 306A or 306B.

Programmable switching block 500 can comprise a set of first signal lines 502 (e.g. signal inputs or signal outputs) intersecting a set of second signal lines 504 (e.g. signal inputs or signal outputs). Moreover, a RRAM junction cell is formed at respective junctions of first signal lines 502 and second signal lines 504. In at least one aspect, the RRAM junction cells can correspond with the junction cell schematic 506.

The RRAM junction cell is configured, in an activated or programmed state, to electrically connect a first signal line and a second signal line at a particular junction, and in a deactivated or erased state, to electrically isolate the first signal line and the second signal line. A connected junction is a programmed junction, depicted by a black square at the respective junction. An isolated junction is an open junction, depicted by a white square at the respective junction.

It should be appreciated that respective junctions of programmable switching block 500 can be reprogrammed (e.g., by changing activation/deactivation states of configuration cells positioned at the respective junctions). Thus, although a particular program state is depicted by the connected junctions and open junctions of FIG. 5, the depicted example is only one possible program state for programmable switching block 500. Further, it should be understood that programmable switching block can be reprogrammed in the field, for FPGA applications.

In addition to the foregoing, in at least some aspects of the subject disclosure, programmable switching block 500 can have bidirectional first signal lines and second signal lines. Said differently, one (or more) of first signal lines 502 can initiate a signal, which can be received at a corresponding one (or more) of second signal lines 504, or one (or more) of second signal lines 504 can initiate a signal, which can be received at a corresponding one (or more) of first signal lines 502. As described herein, whether this signal is received or not received at the first signal line or second signal line is determined from a configuration state of an associated RRAM configuration cell. If the associated RRAM configuration cell is configured as a closed circuit, the signal can be received at the corresponding signal line; otherwise, the signal is not received. Therefore, although programmable switching block 500 identifies respective first signal lines 502 and second signal lines 504, it should be appreciated that in the above-described aspects first signal lines 502 and second signal lines 504 can be renamed signal contacts 505 (not depicted) having a first end 505A and second end 505B, that can be employed for either transmitting or receiving a signal, or both, under suitable conditions (e.g., signals of different frequency, phase, or other suitable distinguishing characteristic could be transmitted concurrently at first end 505A and second end 505B, and received at the corresponding other end 505B and 505A, respectively).

FIG. 6 illustrates a schematic diagram of an example subset of a programmable switching block 600 according to aspects of the subject disclosure. Particularly, programmable switch block 600 comprises four different memory cells at four respective switching block junctions, including cell 0-0 602A, 1-0 602B, 0-1 602C and 1-1 602D (referred to collectively as cells 602A-602D). The naming convention for cells 602A-602D indicate a column number as a first identifier followed by a row number as a second identifier. Thus, cell 1-0 refers to a cell in column 1 and row 0, and cell 0-1 refers to a cell in column 0 and row 1.

Respective cells 602A-602D comprise respective RRAM-based configuration cells. In at least one aspect of the subject disclosure, the RRAM-based configuration cells can be substantially similar to RRAM configuration cell 100. A pass gate transistor of the RRAM-based configuration cells is interposed between respective junctions of input signal columns and output signal rows. This arrangement enables respective pass gate transistors to activate or deactivate the respective junctions. Thus, a junction of input_column₁ 604 and output_row₀ 608 is controlled (e.g., activated or deactivated) by the pass gate transistor of 1-0 cell 602B. Likewise, a junction of input_column₀ 606 and output_row₀ 608 is controlled by the pass gate transistor of 0-0 cell 602A, a junction of input_column₁ 604 and output_row₁ 610 is controlled by the pass gate transistor of 1-1 cell 602D, and a junction of input_column₀ and output_row₁ 610 is controlled by 0-1 cell 602C.

Respective program transistors associated with row₀ and row₁ are activated and deactivated by voltages applied at programming_row₀ 616, and by programming_row₁ 618, respectively. A voltage applied at programming_column₁ 612 is passed to a common node of the voltage divider of 1-0 cell 602B when row₀ program transistors are activated by programming_row₀ 616. Likewise, a voltage applied at programming_column₀ 614 is passed to a common node of the voltage divider of 0-0 cell 602A when row₀ program transistors are activated. Thus, programming/erasing row₀ voltage dividers is accomplished by applying an activation voltage (e.g., three volts) at programming_row₀ 616, and applying suitable program or erase voltages at programming_column₁ 612 (for 1-0 cell 602B) and at programming_column₀ 614 (for 0-0 cell 602A). Moreover, a pull up voltage source 620 applies a voltage to respective pull up resistors of voltage dividers in row 0, whereas a pull up voltage source 624 applies a voltage to respective pull up resistors of voltage dividers in row 1. Pull down activation contact 617 can activate or deactivate a row₀ pull down transistor, enabling a voltage applied at a pull down source 622 to be applied to pull down resistors of voltage dividers in row 0. Likewise, pull down activation contact 619 can activate or deactivate a row₁ pull down transistor, enabling a voltage applied at pull down source 626 to be applied to pull down resistors of voltage dividers in row 1.

In addition to the foregoing, a read enable circuit is provided that facilitates application of a V_(CC) voltage to the pull up resistors of cells 602A-602D. The read enable circuit comprises a read enable voltage source 630. Additionally, the read enable circuit comprises respective PMOS transistors 632. A drain of the respective PMOS transistors 632 is connected to respective pull up transistors of voltage dividers in row 0, as depicted.

Various operating examples of switching block 600 are depicted at FIGS. 7-11, infra. Unless otherwise indicated, element/component numbering of switching block 600 applies as described above to each of FIGS. 7-11. Where a single component has one reference number in FIG. 6 and another reference number in respective ones of FIGS. 7-11, the FIG. 6 reference number indicates a name or identifier of a circuit component, whereas reference numbers of FIGS. 7-11 indicate respective voltages at those circuit components. Thus, the single component should be construed to have both the characteristics of the respective FIGS. 7-11 (e.g., respective voltages), as well as characteristics identified above for switching block 600 (e.g., circuit component name or identifier). As an example, pull down voltage source 622 has the label 0V 706 in FIG. 7. This indicates that the particular component (voltage source) is both a pull down voltage source and has 0 volts applied to that voltage source for the row₀ programming operation of FIG. 7. However, in FIG. 9, pull down voltage source 622 has high voltage HV 904 applied thereto, and thus the row₀ erase operation of FIG. 9 should not be construed to have zero volts applied to pull down voltage source 622.

FIG. 7 illustrates an example schematic diagram 700 of a row programming operation for the programmable switching block 600 using RRAM resistors in a forward polarity configuration, or row erase operation for the programmable switching block 600 using RRAM resistors in a reverse polarity configuration. Particularly, the row programming operation involves programming for row₀ using forward polarity RRAM resistors. As depicted, a common-collector voltage (V_(CC)) 702 can be applied to read enable contact 630 (which deactivates read-enable PMOS). Further, a high voltage HV 704 (e.g., a program voltage) can be applied where indicated, for instance at program_column₁, pull up voltage sources, and program_row₀. Likewise, zero voltage 0V 706 can be applied where indicated, for instance at program_column₀, pull down voltage sources, and program_row₁. Application of zero voltage at program_row₁ deactivates program transistors of memory cells in row₁ (the bottom cells, 1-1 602D and 0-1 602C), and isolates pull up resistors of row₁ from HV 704 applied at pull up voltage source 624.

Assuming that all RRAM resistors are in an erase state (high resistance state), high voltage HV 704 is applied to program_row₀, which is applied directly to program transistor gates of row₀, activating those program transistors, and also enables the HV 704 applied at pull up voltage source 620 to be propagated to pull up resistors of row₀. Moreover, high voltage HV 704 is applied at program_column₁ and zero volts 0V 706 is applied at program_column₀. Accordingly, HV 704 is propagated to the common node of the voltage divider in 1-0 cell 602B. The resulting voltage drop across the pull down resistor of 1-0 cell 602B and current 708 in 1-0 cell 602B programs the pull down resistor of 1-0 cell 602B to a low resistance state when the pull down resistor is in a forward polarity configuration. When the pull down resistor is in a reverse polarity configuration, the voltage drop erases the pull down resistor to a high resistance state. In contrast, a low voltage drop (e.g., about zero volts) across both terminals of the pull up resistor maintains the pull up resistor in a current state (its initial erased state), which is the erased state in this example. Using forward polarity resistors, the high resistance state of the pull up resistor and low resistance state of the pull down resistor deactivates the pass gate transistor of 1-0 cell 602B during normal read operation.

Zero voltage 0V 706 at program_column₀ is applied at the common node of the voltage divider of 0-0 cell 602A. The resulting voltage drop across the pull up resistor of 0-0 cell 602A and the current 710 in 0-0 cell 602A programs the pull up resistor to low resistance, whereas about zero volts applied to both terminals of the pull down resistor (at pull down source 622 and programming column₀ 614) maintains the pull down resistor in the erased state (since all pull down and pull up resistors start in the erased state for the row₀ programming operation of FIG. 7) resulting in high resistance for the pull down resistor when the pull up resistor is in a forward polarity configuration. When the pull up resistor is in a reverse polarity configuration, the voltage drop erases the pull up resistor to a low resistance state. Using forward polarity resistors, high resistance in the pull down resistor and low resistance in the pull up resistor of 0-0 cell 602A activates the pass gate transistor of that cell during normal read operation (e.g., see FIG. 11, infra, for an example read operation), as described herein.

FIG. 8 illustrates a sample schematic diagram 800 of an additional row programming operation for programmable switching block 600 using RRAM resistors in a forward polarity configuration, or additional row erase operation for the programmable switching block 600 using RRAM resistors in a reverse polarity configuration. Particularly, schematic diagram 800 depicts a row programming operation for row₁ using forward polarity RRAM resistors. For programming_row₁ 618, V_(CC) 802 is applied to read enable contact 630, which deactivates read-enable PMOS transistors 632. HV 804 is applied to programming_column₀ 614, to pull up resistor voltage sources 620 and 624 and pull down activation contact 619 and to programming_row₁ 618. About zero volts 0V 806 is applied to pull down resistor voltage sources 622 and 626, pull down activation contact 617, programming_row₀ 616 and to programming_column₁ 612.

Each RRAM resistor in the respective cells 602C-602D is in an erased state prior to application of the voltages listed in schematic diagram 800. The ˜zero volts 0V 806 applied to programming_row₀ 616 deactivates program transistors of row₀, resulting in no voltage being driven at common nodes of the voltage dividers of 0-0 cell 602A and 1-0 cell 602B. Moreover, 0V 806 applied to programming row₀ 616 deactivates the pull up transistor of row₀, such that no voltage is applied to the pull up resistors of row₀. Finally, 0V 806 applied at pull down activation source 617 isolates pull down resistors of row₀ from pull down source 622. Because no voltage is applied to nodes of the voltage divider, row₀ voltage dividers remain unchanged and in their initial erased states or previously programmed state.

With regard to row₁, high voltage HV 804 applied to programming_row₁ 618 activates program resistors of row₁. The program resistor of 1-1 cell 602D transfers 0V 806 to the common node of the voltage divider of 1-1 cell 602D. In addition, HV 804 applied at pull up source 624 results in a voltage drop across the pull up resistor of this cell that is approximately equal to HV 804. This voltage drop and the resulting current 808 of 1-1 cell 602D programs the pull up resistor of 1-1 cell 602D to low resistance when the pull up resistor is in a forward polarity configuration. When the pull up resistor is in a reverse polarity configuration, the voltage drop erases the pull up resistor to a high resistance state. 0V 806 applied at pull down source 626 results in approximately zero volts across the pull down resistor, maintaining the pull down resistor in its initial erased, high resistance state. When using forward polarity resistors, because the pull up resistor of 1-1 cell 602D is programmed and the pull down resistor erased, the pass gate transistor of 1-1 cell 602D will be activated during normal read operation (e.g., see FIG. 11, infra).

In contrast, high voltage HV 804 applied at programming_column₀ 614 results in HV 804 at the common node of the voltage divider of 0-1 cell 602C. In conjunction with HV 804 at pull up source 624, this results in approximately zero volts across the pull up resistor of 0-1 cell 602C, maintaining this pull up resistor in its existing state (the erased state in this example). The 0V 806 applied at pull down source 626 results in a voltage differential of about HV 804 across the pull down resistor of 0-1 cell 602C, leading to the depicted current 810 of this cell and programming the pull down resistor to low resistance when the pull up resistor is in a forward polarity configuration. When the pull up resistor is in a reverse polarity configuration, the voltage drop erases the pull up resistor to a high resistance state. Moreover, this configuration deactivates the pass gate transistor of 0-1 cell 602C during normal read operation.

FIG. 9 and FIG. 10 illustrate example schematic diagrams for respective row erase operations 900 and 1000 for programmable switching block 600 using RRAM resistors in a forward polarity configuration or row programming operation for the programmable switching block 600 using RRAM resistors in a reverse polarity configuration. Row erase operation 900 illustrates such an operation for row₀ following the row₀ programming operation of FIG. 7 using forward polarity RRAM resistors, supra (the pull down resistor and pull up resistor of 1-0 cell 602B are in the program and erase states, respectively, and the pull down resistor and pull up resistor of 0-0 cell 602A are in the erase and program states, respectively). Row erase operation 1000, on the other hand, illustrates a row erase operation for row₁ following the row programming operation of row₁ depicted in FIG. 8 using forward polarity RRAM resistors, supra (the pull down resistor and pull up resistor of 0-1 cell 602C are in the program and erase states, respectively, and the pull down resistor and pull up resistor of 1-1 cell 602D are in the erase and program states, respectively).

As depicted, row erase operation 900 includes a V_(CC) 902 applied at read enable contact 630. This deactivates PMOS transistors 632. In addition, an erase voltage EV 907 is applied to pull down voltage source 622 which is activated with HV 904 applied at pull down activation contact 617. Further, HV 904 is applied to programming_row₀ 616, while EV 907 is also applied to programming_column₀ 614. Approximately zero volts 0V 906 is applied at pull up voltage source 620, pull down activation contact 619, programming_row₁ 618, and to programming_column₁ 612. As described above, 0V 906 applied at programming_row₁ 618 prohibits programmable resistors of row₁ from changing state (e.g., maintaining them in respective initial states prior to implementing the erase operation). The programmed pull down resistor of 1-0 cell 602B, is erased by application of EV 907 to the bottom terminal of this pull down resistor and 0V 906 applied to programming_column₁ 612. The resulting reverse potential difference across the pull down resistor of 1-0 cell 602B and the reverse current 908 generated in this pull down resistor erases the pull down resistor to a high resistance state when the pull down resistor is in a forward polarity configuration. When the pull down resistor is in a reverse polarity configuration, the voltage drop programs the pull down resistor to a low resistance state. The approximately zero volt potential across the pull up resistor of 1-0 cell 602B from 0V 906 at programming_column₁ 612 and at pull up voltage source 620 maintains the pull up resistor in its initial erased state.

Erase voltage EV 907 can be a suitable voltage that, in conjunction with a voltage applied to the common node of the voltage divider of 1-0 cell 602B, results in a potential difference across the pull down transistor that erases the pull down transistor to a high resistance state. Thus, EV 907 can vary depending on a type of RRAM technology employed for the pull down resistor (or pull up resistor when erasing the pull up resistor). For unipolar RRAM technology, a suitable positive potential difference distinct from HV 904 is generally employed for erasing the pull down resistor to the high resistance state. For bipolar RRAM technology, a potential difference that can be similar in magnitude to HV 904 but opposite in polarity is generally suitable for erasing the pull down resistor to the high resistance state (in the forward polarity configuration). Other voltages will be suitable for other RRAM technology, as is known in the art or made known to one of ordinary skill in the art by way of the context provided herein. Such other voltages and RRAM technologies are generally considered within the scope of the subject disclosure.

Regarding 0-0 cell 602A, EV 907 is applied to programming_column₀ 614. This results in no significant potential difference across the pull down resistor of 0-0 cell 602A, as the pull down resistor observes the EV 907 at its upper and lower terminals (the latter being applied at pull down voltage source 624 and activated by HV 904 applied at pull down activation source 617). Accordingly, the pull down resistor of 0-0 cell 602A does not change state. The pull up resistor of 0-0 cell 602A, on the other hand, observes 0V 906 at its upper terminal applied at pull up voltage source 620, and EV 907 applied at programming_column₀ 614, which causes a reverse current 910 through this pull up resistor, erasing the pull up resistor to the high resistance state when the pull up resistor is in a forward polarity configuration. When the pull up resistor is in a reverse polarity configuration, the voltage drop programs the pull up resistor to a low resistance state. Following erase operation 900, the pull up and pull down resistors of 0-0 cell 602A and 1-0 cell 602B can be in their original factory settings (e.g., erased state).

Turning to row erase operation 1000, V_(CC) 1002 is applied at read enable contact 630 to deactivate PMOS transistors 632, and erase voltage EV 1007 is applied at pull down voltage source 626 which is activated with high voltage HV 1004 applied to pull down activation contact 619. HV 1004 is also applied at programming_row₁ 618, while EV 1007 is applied at programming_column₁ 612. Approximately zero volts 0V 1006 is applied at pull up voltage source 624 and to pull down activation contact 617, programming_row₀ 616 and programming_column₀ 614. Row₀ program transistors are deactivated, leaving the initial erase states of the voltage dividers of 0-0 cell 602A and 1-0 cell 602B unchanged. HV 1004 at programming_row₁ 618 activates program transistors of row₁. EV 1007 applied at programming_column₁ 612 and at pull down voltage source 626 results in approximately zero voltage differential across the pull down resistor of 1-1 cell 602D, leaving this pull down resistor in its initial erase state. In contrast, 0V 1006 applied at pull up voltage source 624 and the EV 1007 applied at programming_column₁ 612 results in a potential difference approximately of EV 1007 across the pull up resistor of 1-1 cell 602D and current 1008, erasing this pull up resistor when the pull up resistor is in a forward polarity configuration. When the pull up resistor is in a reverse polarity configuration, the voltage drop programs the pull up resistor to a low resistance state. 1-1 cell 602D is therefore in its initial factory setting after the depicted row erase operation (e.g., the pull up resistor and pull down resistor in the erase state). 0-1 cell 602C observes approximately zero volts at the common node of the pull up and pull down resistors of this cell. Accordingly, approximately zero volts applied at pull up voltage source 624 results in substantially no voltage dropped across the pull up resistor of 0-1 cell 602C, maintaining this resistor in its previous erase state. The EV 1007 applied at pull down voltage source 626 results in a voltage drop across the pull down resistor of 0-1 cell 602C, and the depicted current 1010. The voltage drop and current erases this pull downresistor to be in a low resistance state when the pull down resistor is in a forward polarity. When the pull down resistor is in a reverse polarity configuration, the voltage drop programs the pull down resistor to a low resistance state.

Using forward polarity resistors, embodiments leave the pull up and pull down resistors of 0-1 cell 602C in the erase state (e.g., initial factory setting).

FIG. 11 illustrates a schematic diagram of an example read/active mode operation 1100 for programmable switching block 600 according to one or more further aspects of the subject disclosure. Programmable switching block 600 is in an initial state that corresponds to the programming of row₀ and of row₁ as described above at FIGS. 7 and 8. Thus, pass gate transistors of 0-0 cell 602A and of 1-1 cell 602D are activated in response to programming of the pull up resistors of these cells. Further, the pass gate transistors of 0-1 cell 602B and 1-0 cell 602C are deactivated in response to programming of the pull down resistors of these cells.

To implement the read operation, V_(CC) 1102 is applied at pull down activation contacts 617 and 619, and as a result the zero volts applied at pull down sources 622 and 626 are transferred to the lower contacts of the pull down resistors of row₀ and row₁. The pull up transistors are deactivated in response to zero volts being applied at programming_row₀ 616 and at programming_row₁ 618. However, read-enable PMOS transistors 632 are activated by zero volts applied at read-enable contact 630, and V_(CC) 1102 applied at respective source nodes of read-enable PMOS transistors 632 is therefore observed at the upper contacts of the pull up resistors of row₀ and row₁. Program transistors of row₀ and row₁ are deactivated, and thus the respective voltage dividers observe only V_(CC) at the upper contact, and zero volts at the lower contact, maintaining respective pull up and pull down resistors in their existing states.

In response to voltage settings described above, the pass gate transistors of 0-0 cell 602A and 1-1 cell 602D are activated, and in a conductive state 1108, while the pass gate transistors of 1-0 cell 602B and 0-1 cell 602C are deactivated, and in a non-conductive state 1110, as depicted. Accordingly, because 1-1 cell 602D and 0-0 cell 602A are configured to be active, signal input 604 is electrically connected with signal output 610 at 1-1 cell 602D, and signal input 606 is electrically connected with signal output 608 at 0-0 cell 602A. Current flow (in this case, signal current) is depicted by the dashed lines for the connected signal inputs, e.g., from signal input 604 through the pass gate transistor of 1-1 cell 602D, and out signal output 610, and also from signal input 606 through the pass gate transistor of 0-0 cell 602A and out signal output 608. Because 0-1 cell 602C and 1-0 cell 602B are configured to be inactive, signal input 604 is electrically isolated from signal output 608, and signal input 606 is electrically isolated from signal output 610.

In should also be appreciated that in some aspects of the subject disclosure, the programmable switching block of FIG. 11 can have bidirectional signal contacts (e.g., see FIG. 5, supra). Thus, for instance, signal propagation (current flow) through 1-1 cell 602D could be originated at signal output 610 and received at signal input 604, in these aspects. Likewise, signal propagation through 0-0 cell 602A can be initiated at signal output 608 and received at signal input 606, according to these aspects. Accordingly, the example of read/active mode operation 1100 depicted in FIG. 11 should not be construed to limit the direction of signal propagation to that depicted by this example.

In some of the disclosed embodiments, (e.g., utilizing the voltage divider 200 of FIG. 2 in controlling a passgate transistor element, as depicted in FIG. 1 with voltage divider 200 and transistor element 102) there are two potential issues that can occur. The first issue is the potential for leakage current through the voltage divider 104 from V_(CC) to V_(SS) when high voltage (e.g. read voltage) is applied at V_(CC) and low voltage (e.g. ground) is applied at V_(SS). For example, this leakage current can be on the order of nanoamps or hundreds of nanoamps. When there are thousands or millions of RRAM configuration cells 100 with voltage dividers 104 in an FPGA, the leakage current can become significant. When of sufficient magnitude, the leakage current may cause a disturbance of one or more configuration cells (e.g., an unintentional change of the state of a transistor element 102, for example from conducting to non-conducting or vice versa).

The second issue is that a positive voltage is generally maintained at V_(CC) for the voltage divider 104 in order to maintain the state of transistor element 102. Under continuous read voltage, there is the possibility of a read disturbance occurring which can cause the transistor element 102 to intermittently change state. Moreover, power consumption is higher for an FPGA that applies continuous power to configuration cells of the FPGA.

In order to mitigate these issues, another embodiment can introduce a cell state retention circuit 1212 (or latch 1216) between a programming input (e.g., voltage divider 104) and transistor element 102 that can maintain a state of transistor element 102. Further, the cell state retention circuit 1212 can isolate the gate node of transistor element 102 from the programming input. As a result, the read voltage applied to voltage divider 104 need not be continuously maintained, reducing power consumption of the FPGA as well as reducing disturbances to RRAM cells 104A and 104B due to read voltage being continuously applied to the cells.

Referring to FIG. 12, there is depicted another embodiment of an RRAM configuration cell 1200 that adds cell state retention circuit 1212 to RRAM configuration cell 100 between voltage divider 104 and transistor element 102. Cell state retention circuit 1212 includes latch enable transistor 1218 that is connected to the common node of voltage divider 104 at a first terminal of a channel region of latch enable transistor 1218, and is connected at a second terminal of the channel region of latch enable transistor 1218 to a first terminal of a latch 1216 (e.g. an SRAM cell). The second terminal of latch 1216 is connected to the gate of transistor element 102 and to a first terminal of a channel region of reset transistor 1220, which is activated and deactivated at a reset input 1214. A second terminal of the channel region of reset transistor 1220 is connected to a low voltage (e.g. ground). Latch 1216 comprises inverter 1216A cross coupled with inverter 1216B.

Voltage divider 104 is programmed as discussed above, and can serve as a storage cell for cell state retention circuit 1212 (e.g., when latch enable 1206 is deactivated). However, in order to drive the gate of transistor element 102 under read voltage (as described above with respect to voltage divider 104), latch 1216 must be latched to the voltage state as determined by the programmed voltage divider 104. To this end, V_(CC) (e.g. high voltage or read voltage) is applied at pull up resistor 104A and V_(SS) (e.g. low voltage or ground) is applied at pull down resistor 104B, as well as, latch enable voltage 1206 (e.g. high voltage) is applied at the gate of latch enable transistor 1218. This will enable conductivity through latch enable transistor 1218 thereby setting the voltage state of the common node of voltage divider 104 into latch 1216, the output of which drives the gate of transistor element 102. This will require latch enable transistor 1218 to be conducting for a sufficient amount of time to set the state of latch 1216 with the voltage state of the common node of voltage divider 104, which in a non-limiting example can be approximately 100 nanoseconds or any other suitable amount of time. After latch 1216 has been set with the voltage state of the common node of voltage divider 104, Latch enable voltage 1206 (e.g. high voltage) is removed to deactivate latch enable transistor 1218, thereby isolating the latch 1216 from voltage divider 104. Then application of V_(CC) (e.g. high voltage or read voltage) is removed at pull up resistor 104A and application of V_(SS) (e.g. low voltage or ground) is removed at pull down resistor 104B. Latch enable transistor 1218 is deactivated before removal of application of V_(CC) and V_(SS) to prevent the latch from inadvertently switching states, which could occur if V_(CC) and V_(SS) were removed prior to latch 1216 being isolated from voltage divider 104. For example, if latch 1216 were set to a high voltage state, and application of V_(CC) and V_(SS) were removed prior to deactivation of latch enable transistor 1218, latch 1216 may switch to a low voltage state as a result of low voltage at the common node of voltage divider 104.

With the output of latch 1216 driving the gate of transistor element 102 and the voltage divider 104 being isolated from the gate of transistor element 102, any leakage current or read disturbances from voltage divider 104 are isolated from the gate of transistor element 102. Furthermore, by removing application of V_(CC) and V_(SS) from voltage divider 104, leakage current and read disturbances are mitigated or avoided at voltage divider 104. Accordingly, RRAM configuration cell 1200 can reduce leakage current and disturbance effects on transistor element 102.

It can also be beneficial to place the latch 1216 in a known state prior to programming of the latch 1216. With latch enable transistor 1218 deactivated, a reset voltage (e.g. high voltage) is applied at reset input 1214 to the gate of reset transistor 1220 thereby putting reset transistor 1220 into a conducting state, which will force the second terminal of latch 1216 (and the gate of transistor element 102) to drain to ground and go into a low voltage state. By the nature of latch 1216, forcing the second terminal to drain to ground will also cause the first terminal of latch 1216 to be in a high state. Thus, reset transistor 1220 can be utilized to force a known state on latch 1216 (e.g., high at the first terminal of latch 1216, and low at the second terminal of latch 1216). Reset transistor 1220 is deactivated during programming or operation of latch 1216. Latch 1216 can then be programmed via activation of latch enable transistor 1218 and control of voltage divider 104, as described herein.

Another advantage provided by RRAM configuration cell 1200 is that the transistor 1218 isolates the voltage divider 104 from latch 1216 and the ability to program voltage divider 104 with a new state while latch 1216 is driving the gate of transistor element 102 with a previous state. An FPGA switching block can be reprogrammed with a new set of values by changing activation/deactivation states of transistor elements 102 at each junction of the bitlines and wordlines of the switching block while the FPGA is in operation with the previously programmed set of values. Since latch 1216, once programmed, can be isolated from voltage divider 104 by latch enable transistor 1218, voltage divider 104 can be reprogrammed to a new state using the programming mechanism described herein. When the new state of voltage divider 104 is to be programmed into latch 1216, V_(CC) is applied at pull up resistor 104A and V_(SS) is applied at pull down resistor 104B as described herein (e.g., high voltage at V_(CC) and low voltage or ground at V_(SS)), and latch enable voltage 1206 is set high to activate latch enable transistor 1218, as described above. The voltage state of the common node of voltage divider 104 is thereby input into the first terminal of latch 1216. After latch 1216 has been set with the voltage state of the common node of voltage divider 104, application of latch enable voltage 1206 (e.g. high voltage) is removed at the gate of latch enable transistor 1218, thereby isolating the latch 1216 from voltage divider 104. Then application of V_(CC) (e.g. high voltage or read voltage) is removed at pull up resistor 104A and application of V_(SS) (e.g. low voltage or ground) is removed at pull down resistor 104B. Optionally, latch 1216 can be reset prior to programming. In this manner, the FPGA can be preprogrammed at the voltage dividers 104 with a next set of values for the array, which can be implemented at the junctions at a desired time through reprogramming of the latches 1216 of the RRAM configuration cells 1200.

FIG. 13 depicts another embodiment of an RRAM configuration cell 1300 similar to RRAM configuration cell 1200, where cell state retention circuit 1212 of RRAM configuration cell 1200 is replaced by cell state retention circuit 1312, and voltage divider 104 of RRAM configuration cell 1200 is replaced with storage cell 1304. In storage cell 1304, pull up resistor 1304A can function substantially similar to pull up resistor 104A of voltage divider 104, and pull down transistor 1304B replaces pull down resistor 104B. A first terminal of a channel region of pull down transistor 1304B is connected to a terminal of pull up resister 104A and also connected to program contact 408 of program transistor 402. A second terminal of the channel region of pull down transistor 1304B is connected to a V_(SS) voltage connection. Pull down transistor 1304B in operation of RRAM configuration cell 1300 will act as pull down resistor 104B does in operation of RRAM configuration cell 1200, however instead of programming the state of pull down resistor 104B in RRAM configuration cell 1200, pull down transistor 1304B provides direct control of the conducting state of pull down transistor 1304B through application of a Read Enable voltage 1302 at the gate of pull down transistor 1304B (e.g. high voltage for high conductance, low voltage for low conductance where an NMOS transistor is employed for pull down transistor 1304B, although the subject disclosure is not so limited). For example, application of Read Enable voltage 1302 places pull down transistor 1304B into a conducting state, analogous to pull down resistor 104B being in a conducting state (though pull down transistor 1304B can be selected to have different resistance or the same or similar resistance in the conducting state as compared with pull down resistor 104B, in various embodiments). Therefore, in embodiments described above where pull down resistor 104B is in a conducting state, equivalently a Read Enable voltage 1302 would be applied at the gate of pull down transistor 1304B such that pull down transistor 1304B is conducting, and in embodiments described above where pull down resistor 104B is in a non-conducting state, equivalently a Read Enable voltage 1302 would not be applied (or a low voltage or ground is applied in the embodiment where pull down transistor 1304B is an NMOS device) at the gate of pull down transistor 1304B such that pull down transistor 1304B is non-conducting.

Latch 1316 comprises four transistors 1316A, 1316B, 1316C, and 1316D. The gates of transistors 1316A and 1316C are connected to the gate of transistor element 102 and to reset transistor 1220, as illustrated. The gates of transistors 1316B and 1316D are connected to the second terminal of the channel region of latch enable transistor 1218, as illustrated. A first terminal of a channel region of transistor 1316A and a first terminal of a channel region of transistor 1316B are connected to each other and a V_(DD) voltage connection. A second terminal of the channel region of transistor 1316A is connected to a first terminal of a channel region of transistor 1316C, which shares a node with the gates of transistors 1316B and 1316D and the output of latch enable transistor 1218. A second terminal of the channel region of transistor 1316B is connected to a first terminal of a channel region of transistor 1316D, which shares a second node with the gate of transistor element 102, reset transistor 1220 and the gates of transistors 1316A and 1316C. A second terminal of the channel region of transistor 1316C and a second terminal of a channel region of transistor 1316D are connect to each other and to ground. Latch 1316 can be operated (e.g., programmed and reset) in the manner as latch 1216 described above, in an embodiment(s).

RRAM configuration cell 1300 also has the ability whereby storage cell 1304 can be programmed with a new state while latch 1316 is driving the gate of transistor element 102 with a previous state, similar to RRAM configuration cell 1200.

FIG. 14 depicts another embodiment of an RRAM configuration cell 1400 similar to RRAM configuration cell 1200 with two voltage dividers 1402 and 1404 in place of voltage divider 104. This arrangement allows for having multiple preprogrammed sets of values for the FPGA that can be quickly implemented in the array at desired times. Voltage divider 1 1402 and voltage divider 2 1404 can each be independently programmed in the manner described above for programming voltage divider 104. Also, voltage divider 1 1402 or voltage divider 2 1404 can be programmed into latch 1216 in the manner described above for programming the state of voltage divider 104 into latch 1216. For example, if a first set of values of an FPGA array are stored in voltage dividers 1 1402 of RRAM configuration cell 1400 and a second set of values of an FPGA array are stored in voltage dividers 2 1402 of RRAM configuration cells 1400, latches 1216 of RRAM configuration cells 1400 can be programmed with either the first set of values or the second set of values based upon application voltages (V_(cc1) and V_(ss1)) or (V_(cc2) and V_(ss2)). It is to be appreciated that while only two voltage dividers 1402 and 1404 are depicted in RRAM configuration cell 1400, any number of voltage dividers can be implemented in RRAM configuration cell 1400 allowing for any number of preprogrammed sets of values for the FPGA.

FIG. 15 depicts another embodiment of an RRAM configuration cell 1500 similar to RRAM configuration cell 1300 with two storage cells 1504 and 1506 in place of storage cell 1304. Similar to RRAM configuration cell 1400, this arrangement allows for having multiple preprogrammed sets of values for the FPGA that can be quickly implemented in the array at desired times. Storage cell 1 1504 and storage cell 2 1506 can each be independently programmed in the manner described above for programming storage cell 1304. Also, storage cell 1 1504 and storage cell 2 1506 can be programmed into latch 1316 in the manner described above for programming the state of storage cell 1304 into latch 1316. For example, if a first set of values of an FPGA array are stored in storage cells 1 1504 of RRAM configuration cell 1500 and a second set of values of an FPGA array are stored in storage cells 2 1506 of RRAM configuration cells 1500, respective latches 1316 of RRAM configuration cells 1500 can be programmed with either the first set of values or the second set of values based upon application of respective storage cell voltages (V_(cc1), V_(ss1), and Read Enable 1 as appropriate) or (V_(cc2), V_(ss2), and Read Enable 2 as appropriate), and latch enable voltage 1206. It is to be appreciated that while only two storage cells 1504 and 1506 are depicted in RRAM configuration cell 1500, any number of voltage dividers can be implemented in RRAM configuration cell 1500 allowing for any number of preprogrammed sets of values for the FPGA.

The aforementioned diagrams have been described with respect to interaction between several components, or memory architectures. It should be appreciated that such diagrams can include those components and architectures specified therein, some of the specified components/architectures, and/or additional components/architectures. For example, a memory cell architecture could include a combination of voltage divider component 200, programming circuit component 400, in conjunction with transistor element 102, signal input 110 and signal output 108. Sub-components could also be implemented as electrically connected to other sub-components rather than included within a parent architecture. Additionally, it should be noted that one or more disclosed processes could be combined into a single process providing aggregate functionality. For instance, a program process can comprise an erase process, or vice versa, to facilitate programming and erasing a semiconductor cell by way of a single process. In addition, it should be appreciated that respective rows of disclosed switching blocks can be programmed or erased in groups (e.g., multiple rows programmed or erased concurrently) or individually. Components of the disclosed architectures can also interact with one or more other components not specifically described herein but known by those of skill in the art.

In view of the exemplary diagrams described supra, process methods that can be implemented in accordance with the disclosed subject matter will be better appreciated with reference to the flow charts of FIGS. 16-22. While for purposes of simplicity of explanation, the methods 1600, 1700, 1800, 1900, 2000, 2100 and 2200 are shown and described as a series of blocks, it is to be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in different orders and/or concurrently with other blocks from what is depicted and described herein. Moreover, not all illustrated blocks may be required to implement the methods 1600, 1700, 1800, 1900, 2000, 2100 and 2200 described hereinafter. Additionally, it should be further appreciated that the methods 1600, 1700, 1800, 1900, 2000, 2100 and 2200 disclosed hereinafter and throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such methodologies to an electronic device. The term article of manufacture, as used, is intended to encompass a computer program accessible from any computer-readable device, device in conjunction with a carrier, or storage medium.

FIG. 16 illustrates a flowchart of an example method 1600 for fabricating a programmable switching block, according to aspects of the subject disclosure. At 1602, method 1600 can comprise forming an electrical junction between a signal input and a signal output of the programmable switching block. At 1604, method 1600 can comprise forming a RRAM cell at the electrical junction. The RRAM cell can comprise a transistor element that physically connects the signal input with the signal output. According to particular aspects of the subject disclosure, the RRAM cell can further comprise multiple programmable resistive elements. In at least one aspect, the multiple programmable resistive elements can form a voltage divider that drives a gate of the transistor element. At 1606, method 1600 can comprise forming a programming circuit configured to activate or deactivate the RRAM cell thereby activating or deactivating the electrical junction, respectively. In at least one aspect, the programming circuit can be formed independent from the signal input and the signal output of the programmable switching block.

FIG. 17 depicts a flowchart of am example method 1700 for forming a programmable switching block based on RRAM memory cells according to further aspects of the subject disclosure. At 1702, method 1700 can comprise forming a set of signal inputs of the programmable switching block. Further, at 1704, method 1700 can comprise forming a set of signal outputs intersecting the set of signal inputs. At 1706, method 1700 can comprise forming respective RRAM configuration cells at respective junctions of signal inputs and signal outputs of the programmable switching block. At 1708, method 1700 can comprise interposing a transistor element of respective RRAM cells between signal inputs and signal outputs of respective junctions. Moreover, at 1710, method 1700 can comprise forming a programmable voltage divider having programmable pull up and pull down resistors at a gate of each transistor element. At 1712, method 1700 can comprise forming a program transistor at a junction of each pull up or pull down resistor. At 1714, method 1700 can comprise forming program leads to the program transistors and voltage dividers to activate and deactivate respective RRAM configuration cells, thereby controlling configuration of respective junctions of the programmable switching block.

FIG. 18 illustrates a flowchart of an example method 1800 for fabricating a programmable switching block, according to aspects of the subject disclosure. At 1802, method 1800 can comprise forming an electrical junction between a signal input and a signal output of the programmable switching block. At 1804, method 1800 can comprise forming a RRAM configuration circuit at the electrical junction. The RRAM configuration circuit can comprise a transistor element that electrically connects or disconnects the signal input with the signal output. According to particular aspects of the subject disclosure, the RRAM configuration circuit can further comprise a cell state retention circuit that drives a gate of the transistor element. In at least one embodiment, forming the cell state retention circuit can comprise forming a latch having an output terminal connected to a gate of the transistor element, and having an input terminal. According to other particular aspects of the subject disclosure, forming the RRAM configuration circuit can further comprise forming a storage cell comprising multiple programmable resistive elements. In at least one aspect, the multiple programmable resistive elements can form a voltage divider that selectively drives the input terminal of the latch of the cell state retention circuit in response to an activation signal(s). At 1806, method 1800 can comprise forming a programming circuit configured to program or erase one or more of the programmable resistive elements and thereby update a value stored by the storage cell. In at least one aspect, the programming circuit can be formed independent from the signal input and the signal output of the programmable switching block.

FIG. 19 illustrates a flowchart of an example method 1900 for fabricating a programmable switching block, according to aspects of the subject disclosure. At 1902, method 1900 can comprise forming an electrical junction between a signal input and a signal output of the programmable switching block. At 1904, method 1900 can comprise forming a RRAM configuration circuit at the electrical junction. The RRAM configuration circuit can comprise a transistor element that electrically connects or disconnects the signal input with the signal output. According to particular aspects of the subject disclosure, forming the RRAM configuration circuit can further comprise forming a cell state retention circuit having an output that drives a gate of the transistor element. According to other particular aspects of the subject disclosure, forming the RRAM configuration circuit can further comprise forming a plurality of storage cells respectively comprising voltage dividers, and forming respective control inputs to the voltage dividers. In at least one aspect, the respective control inputs facilitate reprogramming of data values stored by respective storage cells. At 1906, method 1900 can comprise forming a latch enable circuit to electrically connect or isolate a selected voltage divider of the voltage dividers with an input of the cell state retention circuit. In conjunction with the latch enable circuit, the respective control inputs can further facilitate loading a selected one of the stored values into a latch of the cell state retention circuit. In at least one aspect, the programming circuit can be formed independent from the signal input and the signal output of the programmable switching block.

FIG. 20 illustrates a flowchart of an example method 1900 for fabricating a programmable switching block, according to aspects of the subject disclosure. At 2002, method 2000 can comprise forming an electrical junction between a signal input and a signal output of the programmable switching block. At 2004, method 2000 can comprise forming a RRAM configuration circuit at the electrical junction. Forming the RRAM cell can further comprise forming a transistor element that electrically connects or disconnects the signal input with the signal output. According to particular aspects of the subject disclosure, forming the RRAM configuration circuit can further comprise forming a cell state retention circuit having an output that drives a gate of the transistor element and having an input that facilitates inputting a new state into the cell state retention circuit. According to other particular aspects of the subject disclosure, forming the RRAM configuration circuit can further comprise forming a storage cell having a resistive element and another transistor element sharing a common node. In at least one aspect, forming the RRAM configuration circuit can further comprise forming control inputs to the storage cell that facilitate re-programming a data value stored at the storage cell. At 2006, method 2000 can comprise forming a programming circuit configured to load a data value stored at the storage cell into the input of the cell state retention circuit. In at least one aspect, the programming circuit can be formed independent from the signal input and the signal output of the programmable switching block.

FIG. 21 illustrates a flowchart of an example method 2100 for fabricating a programmable switching block, according to aspects of the subject disclosure. At 2102, method 2100 can comprise forming an electrical junction between a signal input and a signal output of the programmable switching block. At 2104, method 2100 can comprise forming a RRAM configuration circuit at the electrical junction. The RRAM configuration circuit can comprise a transistor element that electrically connects or disconnects the signal input with the signal output. According to particular aspects of the subject disclosure, forming the RRAM configuration circuit can further comprise forming a cell state retention circuit that drives a gate of the transistor element. According to other particular aspects of the subject disclosure, forming the RRAM configuration circuit can further comprise forming a plurality of storage cells respectively comprising one of multiple programmable resistive elements and one of multiple other transistor elements. In at least one aspect, pairs of the programmable resistive elements and the other transistor elements form respective storage cells of the plurality of storage cells. Additionally, forming the RRAM configuration circuit can further comprise forming respective control inputs to the plurality of storage cells to facilitate programming and reprogramming selected ones of the plurality of storage cells. At 2106, method 2100 can comprise forming a latch enable circuit that, in conjunction with one of the respective control inputs, facilitates loading a data value stored by a selected one of the plurality of storage cells into cell state retention circuit. In at least one aspect, the programming circuit can be formed independent from the signal input and the signal output of the programmable switching block.

FIG. 22 depicts a flowchart of am example method 2200 for forming a programmable switching block based on RRAM memory cells according to further aspects of the subject disclosure. At 2202, method 2200 can comprise forming a set of signal inputs of the programmable switching block. Further, at 2204, method 2200 can comprise forming a set of signal outputs intersecting the set of signal inputs. At 2206, method 2200 can comprise forming respective RRAM configuration circuits at respective junctions of signal inputs and signal outputs of the programmable switching block. At 2208, method 2200 can comprise forming respective programming circuits for the respective RRAM configuration circuits, where one of the programming circuits is configured to modify a data value of a data storage circuit of an associated one of the RRAM configuration circuits, and can comprise forming a latch enable circuit to facilitate selective reprogramming of an associated one of the electrical junctions with the data value of the data storage unit, and to facilitate isolation of the associated one of the electrical junctions from the data storage circuit following the reprogramming.

What has been described above includes examples of the subject innovation. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the subject innovation, but one of ordinary skill in the art can recognize that many further combinations and permutations of the subject innovation are possible. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “includes” “has” or “having” are used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.

Moreover, the word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form.

Additionally, some portions of the detailed description have been presented in terms of algorithms or process operations on data bits within electronic memory. These process descriptions or representations are mechanisms employed by those cognizant in the art to effectively convey the substance of their work to others equally skilled. A process is here, generally, conceived to be a self-consistent sequence of acts leading to a desired result. The acts are those requiring physical manipulations of physical quantities. Typically, though not necessarily, these quantities take the form of electrical and/or magnetic signals capable of being stored, transferred, combined, compared, and/or otherwise manipulated.

It has proven convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise or apparent from the foregoing discussion, it is appreciated that throughout the disclosed subject matter, discussions utilizing terms such as processing, computing, calculating, determining, or displaying, and the like, refer to the action and processes of processing systems, and/or similar consumer or industrial electronic devices or machines, that manipulate or transform data represented as physical (electrical and/or electronic) quantities within the registers or memories of the electronic device(s), into other data similarly represented as physical quantities within the machine and/or computer system memories or registers or other such information storage, transmission and/or display devices.

In order to provide a context for the various aspects of the disclosed subject matter, FIG. 23, as well as the following discussion, is intended to provide a brief, general description of a suitable environment in which various aspects of the disclosed subject matter can be implemented or processed. While the subject matter has been described above in the general context of electronic memory or architectures and process methodologies for fabricating or operating such memory or architectures, those skilled in the art will recognize that the subject disclosure also can be implemented in combination with other architectures or process methodologies. Moreover, those skilled in the art will appreciate that the disclosed processes can be practiced with a processing system or a computer processor, either alone or in conjunction with a host computer, which can include single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as personal computers, hand-held computing devices (e.g., PDA, smart phone, watch), microprocessor-based or programmable consumer or industrial electronics, any of the disclosed field programmable gate arrays devices, and the like. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of the subject innovation can be practiced on stand-alone electronic devices, such as a memory card, Flash memory module, removable memory, or the like. In a distributed computing environment, program modules can be located in both local and remote memory storage modules or devices.

FIG. 23 illustrates a block diagram of an example operating and control environment 2300 for a memory array 2302 of a memory device in one or more disclosed embodiments. In one or more embodiments, memory array 2302 can be one of a plurality of memory arrays of a multi-bank memory device. In at least one aspect of the subject disclosure, memory array 2302 can comprise one or more two-terminal resistive memory cells connected as part of configuration circuits of a field programmable gate array, or can be utilized to store instructions, data or the like for operating such configuration circuits. In various embodiments, memory array 2302 can comprise a two-terminal memory technology, arranged in a compact two or three dimensional architecture. Suitable two-terminal memory technologies can include resistive-switching memory, conductive-bridging memory, phase-change memory, organic memory, magneto-resistive memory, or the like, or a suitable combination of the foregoing.

A column controller 2306 and sense amps 2308 can be formed adjacent to memory array 2302. Moreover, column controller 2306 can be configured to activate (or identify for activation) a subset of bitlines of memory array 2302. Column controller 2306 can utilize a control signal provided by a reference and control signal generator(s) 2318 to activate, as well as operate upon, respective ones of the subset of bitlines, applying suitable program, erase or read voltages to those bitlines. Non-activated bitlines can be kept at an inhibit voltage (also applied by reference and control signal generator(s) 2318), to mitigate or avoid bit-disturb effects on these non-activated bitlines.

In addition, operating and control environment 2300 can comprise a row controller 2304. Row controller 2304 can be formed adjacent to and electrically connected with word lines of memory array 2302. Further, utilizing control signals of reference and control signal generator(s) 2318, row controller 2304 can select particular rows of memory cells with a suitable selection voltage. Moreover, row controller 2304 can facilitate program, erase or read operations by applying suitable voltages at selected word lines.

Sense amps 2308 can read data from, or write data to the activated memory cells of memory array 2302, which are selected by column control 2306 and row control 2304. Data read out from memory array 2302 can be provided to an input and input/output buffer 2312 (e.g., a standard buffer, a non-standard or hybrid standard/non-standard buffer, in some embodiments). Likewise, data to be written to memory array 2302 can be received from the input and input/output buffer 2312 and written to the activated memory cells of memory array 2302.

A clock source(s) 2310 can provide respective clock pulses to facilitate timing for read, write, and program operations of row controller 2304 and column controller 2306. Clock source(s) 2310 can further facilitate selection of wordlines or bitlines in response to external or internal commands received by operating and control environment 2300. Input and input/output buffer 2312 can comprise a command and address input, as well as a bidirectional data input and output. Instructions are provided over the command and address input, and the data to be written to memory array 2302 as well as data read from memory array 2302 is conveyed on the bidirectional data input and output, facilitating connection to an external host apparatus, such as a computer or other processing device (not depicted).

Input and input/output buffer 2312 can be configured to receive write data, receive an erase instruction, receive a status or maintenance instruction, output readout data, output status information, and receive address data and command data, as well as address data for respective instructions. Address data can be transferred to row controller 2304 and column controller 2306 by an address register 2310. In addition, input data is transmitted to memory array 2302 via signal input lines between sense amps 2308 and input and input/output buffer 2312, and output data is received from memory array 2302 via signal output lines from sense amps 2308 to input and input/output buffer 2312. Input data can be received from the host apparatus, and output data can be delivered to the host apparatus via the I/O bus.

Commands received from the host apparatus can be provided to a command interface 2316. Command interface 2316 can be configured to receive external control signals from the host apparatus, and determine whether data input to the input and input/output buffer 2312 is write data, a command, or an address. Input commands can be transferred to a state machine 2320.

State machine 2320 can be configured to manage programming and reprogramming of memory array 2302 (as well as other memory arrays of the multi-bank memory array). Instructions provided to state machine 2320 are implemented according to control logic configurations, enabling state machine 2320 to manage read, write, erase, data input, data output, and other functionality associated with memory array 2302. In some aspects, state machine 2320 can send and receive acknowledgments and negative acknowledgments regarding successful receipt or execution of various commands. In further embodiments, state machine 2320 can decode and implement status-related commands, decode and implement configuration commands, and so on.

To implement read, write, erase, input, output, etc., functionality, state machine 2320 can control clock source(s) 2308 or reference and control signal generator(s) 2318. Control of clock source(s) 2308 can cause output pulses configured to facilitate row controller 2304 and column controller 2306 implementing the particular functionality. Output pulses can be transferred to selected bitlines by column controller 2306, for instance, or wordlines by row controller 2304, for instance.

In regard to the various functions performed by the above described components, architectures, circuits, processes and the like, the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., a functional equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary aspects of the embodiments. In this regard, it will also be recognized that the embodiments include a system as well as a computer-readable medium having computer-executable instructions for performing the acts and/or events of the various processes.

In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “includes,” and “including” and variants thereof are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term “comprising.” 

What is claimed is:
 1. A field programmable gate array (FPGA), comprising: a switching block routing array comprising a plurality of signal inputs and a plurality of signal outputs; a first transistor element coupled to the switching block routing array, wherein the first transistor element comprises a first gate, a first transistor terminal and a second transistor terminal, wherein the first transistor terminal is coupled to a signal input from the plurality of signal inputs, and wherein the second transistor terminal is coupled to a signal output from the plurality of signal outputs, and wherein the first gate is configured to electrically couple or decouple the signal input and the signal output in response to a gate control signal; a latch comprising a first latch terminal and a second latch terminal, wherein the second latch terminal is coupled to the first gate of the first transistor element; a second transistor element comprising a second gate, a third transistor terminal and a fourth transistor terminal; wherein the fourth transistor terminal is coupled to the first latch terminal and the second gate is selectively coupled to an activation voltage; a plurality of resistive elements coupled to the second transistor element, wherein each resistive element from the plurality of resistive elements comprises a first electrode and a second electrode, wherein each resistive element is characterized by a plurality of resistive states including a low resistive state and a high resistive state, wherein the plurality of resistive elements includes a first resistive element and a second resistive element, wherein a first electrode of the first resistive element is selectively coupled to a first voltage source, wherein a second electrode of the second resistive element is selectively coupled to a second voltage source; a shared node coupled to a second electrode of the first resistive element, to a first electrode of the second resistive element, and to the third transistor terminal of the second transistor element, wherein the plurality of resistive elements are configured to provide a set signal at the shared node in response at least to a first resistive state of the first resistive element, to a second resistive state of the second resistive element, a relatively high voltage from the first voltage source, and a relatively low or ground voltage from the second voltage source, wherein the second transistor element facilitates controlling propagation of the set signal to the latch in response to the activation voltage, and the first latch terminal of the latch is configured to become set with the set signal in response to activation of the second transistor and propagation of the set signal to the latch, and the first transistor element is configured to electrically couple the signal input to the signal output in response to the first latch terminal becoming set with the set signal; and a programming circuit coupled to the shared node, wherein the programming circuit is configured to facilitate entry to the first resistive state of the first resistive element or is configured to facilitate entry of the second resistive state of the second resistive element in response to an output path voltage applied by the programming circuit to the shared node.
 2. The field programmable gate array (FPGA) of claim 1, wherein the plurality of resistive elements are further configured to provide an unset signal at the shared node in response at least to a second resistive state of the first resistive element, to a first resistive state of the second resistive element, the voltage from the first voltage source, and to the voltage from the second voltage source, wherein the second transistor element facilitates controlling propagation of the unset signal to the latch in response to the activation voltage, and first latch terminal of the latch is configured to store the unset signal in response to activation of the second transistor and propagation of the unset signal to the latch, and the first transistor element is further configured to electrically decouple the signal input from the signal output in response to the first latch terminal storing the unset signal.
 3. The field programmable gate array (FPGA) of claim 1, wherein the plurality of resistive elements includes a third resistive element and a fourth resistive element, wherein a first electrode of the third resistive element is selectively coupled to a third voltage source, wherein a second electrode of the fourth resistive element is selectively coupled to a fourth voltage source, wherein the plurality of resistive elements are further configured to provide the set signal at the shared node in response at least to a first resistive state of the third resistive element, to a second resistive state of the fourth resistive element, the relatively high voltage from the third voltage source, and the relatively low voltage or ground from the fourth voltage source, and wherein the shared node is further coupled to a second electrode of the third resistive element and a first electrode of the fourth resistive element.
 4. The field programmable gate array (FPGA) of claim 3, wherein the programming circuit is further configured to facilitate entry to the first resistive state of the third resistive element or is configured to facilitate entry of the second resistive state of the fourth resistive element in response to an output path voltage applied by the programming circuit to the shared node.
 5. The field programmable gate array (FPGA) of claim 3, wherein the plurality of resistive elements are further configured to provide an unset signal at the shared node in response at least to a second resistive state of the third resistive element, to a first resistive state of the fourth resistive element, to the voltage from the third voltage source, and to the voltage from the fourth voltage source, wherein the second transistor element facilitates controlling propagation of the unset signal to the first latch terminal in response to the activation voltage, and the first latch terminal is configured to store the unset signal in response to activation of the second transistor and propagation of the unset signal to the first latch terminal, and the first transistor element is further configured to electrically decouple the signal input from the signal output in response to the first latch terminal storing the unset signal.
 6. The field programmable gate array (FPGA) of claim 1, wherein the plurality of resistive elements includes pairs of third resistive elements and fourth resistive elements, wherein for each pair a first electrode of the third resistive element is selectively coupled to a third voltage source, wherein a second electrode of the fourth resistive element is selectively coupled to a fourth voltage source, wherein the plurality of resistive elements are further configured to provide the set signal at the shared node in response at least to one of the pairs of third resistive elements and fourth resistive elements having a first resistive state of the third resistive element, a second resistive state of the fourth resistive element, a voltage from the third voltage source, and a voltage from the fourth voltage source, and wherein the shared node is further coupled to a second electrode of the third resistive element and a first electrode of the fourth resistive element.
 7. The field programmable gate array (FPGA) of claim 6, wherein the plurality of resistive elements are further configured to provide an unset signal at the shared node in response at least to the one pair of the third resistive elements and fourth resistive elements having a second resistive state of the third resistive element, a first resistive state of the fourth resistive element, the voltage from the third voltage source, and the voltage from the fourth voltage source, wherein the second transistor element facilitates controlling propagation of the unset signal to the first latch terminal in response to the activation voltage, and the first latch terminal is configured to store the unset signal in response to activation of the second transistor and propagation of the unset signal to the first latch terminal, and the first transistor element is further configured to electrically decouple the signal input from the signal output in response to the first latch terminal storing the unset signal.
 8. The field programmable gate array (FPGA) of claim 1, wherein the latch comprises a first invertor cross coupled with a second invertor.
 9. The field programmable gate array (FPGA) of claim 1, wherein the latch comprises at least four additional transistor elements.
 10. The field programmable gate array (FPGA) of claim 1, further comprising a third transistor element comprising a third gate, a fifth transistor terminal and a sixth transistor terminal; wherein the fifth transistor terminal is coupled to the second latch terminal, the sixth transistor terminal is coupled to a low voltage, and the third gate is selectively coupled to a reset voltage, wherein the third transistor element facilitates clearing of the latch in response to coupling the third gate to the reset voltage.
 11. A configuration bit for a field programmable gate array (FPGA), comprising: a signal input and a signal output of a switching block routing array of the FPGA; a first transistor configured to electrically couple or decouple the signal input and the signal output in response to a control signal applied at a gate of the first transistor; a latch comprising a first latch terminal and a second latch terminal, wherein the second latch terminal is coupled to the gate of the first transistor and provides the control signal to the gate of the first transistor; a non-volatile storage cell comprising a first resistive switching device and a second resistive switching device sharing a common node; a second transistor configured to selectively couple or decouple the common node with the first latch terminal in response to an activation voltage, wherein the second transistor is deactivated in response to the activation voltage having a low value, and electrically decouples the common node from the first latch terminal of the latch; and a programming circuit coupled to the common node and configured to output a low voltage or a high voltage to the common node to facilitate changing a resistance state at least of the first resistive switching device, wherein a signal provided at the common node by the non-volatile storage cell is loaded to the first latch terminal of the latch in part in response to the activation voltage and the selective coupling of the common node with the first latch terminal by the second transistor.
 12. The field programmable gate array (FPGA) of claim 11, wherein the first resistive switching device comprises a first terminal connected to a first voltage source, and the second resistive switching device comprises a second terminal connected to a second voltage source, and further wherein a second terminal of the first resistive switching device and a first terminal of the second resistive switching device are connected to the common node, wherein the signal provided at the common node by the non-volatile storage cell is loaded to the first latch terminal of the latch in further part in response to a relatively high voltage at the first voltage source or a relatively low voltage at the second voltage source.
 13. The field programmable gate array (FPGA) of claim 12, further comprising a second non-volatile storage cell connected to the common node and at least to a third voltage source, wherein a second signal stored by the second non-volatile storage cell is provided at the common node in response to activation of the third voltage source and deactivation of the first voltage source.
 14. The field programmable gate array (FPGA) of claim 13, wherein the programming circuit is further configured to facilitate changing a second resistance state at least of a third resistive switching device of the second non-volatile storage cell, and a value of the second signal stored by the second non-volatile storage cell, in response to output of the low voltage or the high voltage in conjunction with activation of the third voltage source and grounding a fourth resistive switching device of the second non-volatile storage cell.
 15. The field programmable gate array (FPGA) of claim 11, wherein power applied to the non-volatile storage cell is deactivated in response to deactivation of the second transistor.
 16. The field programmable gate array (FPGA) of claim 15, wherein the first resistive switching device is a two-terminal, non-volatile resistive switching memory device and the second resistive switching device is a third transistor having a drain connected to the common node, a source connected to a voltage source, and a gate connected to a read enable source to facilitate reading a value of the signal provided at the common node.
 17. The field programmable gate array (FPGA) of claim 11, wherein the latch comprises a first invertor cross coupled with a second invertor.
 18. The field programmable gate array (FPGA) of claim 11, wherein the latch comprises at least four additional transistors.
 19. The field programmable gate array (FPGA) of claim 11, further comprising a third transistor having a drain connected to the gate of the first transistor and to the second latch terminal, a source connected to ground, and a gate of the third transistor selectively coupled to a reset voltage, wherein the third transistor facilitates clearing of the latch in response to the reset voltage being coupled to the gate of the third transistor.
 20. The field programmable gate array (FPGA) of claim 13, wherein the second non-volatile storage cell comprises a third resistive switching device having a first terminal thereof connected to the third voltage source and a second terminal thereof connected to the common node, and comprises a fourth resistive switching device having a second terminal thereof connected to a fourth voltage source and a first terminal thereof connected to the common node. 